Non-planar gate all-around device and method of fabrication thereof

• US 9,252,275 B2
• Filed: 12/23/2014
• Issued: 02/02/2016
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Sony Group Corp.
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Pillarisetty, Ravi, Lee, Van H., Kavalieros, Jack T., Chau, Robert S., Kachian, Jessica S.
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US14/582,131
• Publication Number:
  US 20150144880A1
• Time in Patent Office: 406 Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. Channel nanowires having a third lattice are formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires include a bottom-most channel nanowire and a bottom gate isolation is formed on the top surface of the substrate under the bottom-most channel nanowire. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding each channel nanowire.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising a first material, the first material having a first lattice constant;

a source region above the substrate, the source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;

a drain region above the substrate, the drain region comprising the second material;

a first nanowire, the first nanowire being coupled to the source region and being coupled to the drain region, the first nanowire comprising a third material, the third material having a third lattice constant substantially the same as the second lattice constant;

a second nanowire above the first nanowire and not in direct contact with the first nanowire, the second nanowire being coupled to the source region and being coupled to the drain region, the second nanowire comprising the third material;

a gate dielectric layer around at least a portion of the first nanowire and around at least a portion of the second nanowire; and

a gate electrode around at least a portion of the first nanowire and around at least a portion of the second nanowire, the gate electrode being separated from the first and second nanowires by at least the gate dielectric layer.

2. The device of claim 1, wherein the second lattice constant is larger than the first lattice constant.

3. The device of claim 1, wherein the second material is the same as the third material.

4. The device of claim 1, wherein the source region and the drain region both have side walls that are angled.

5. The device of claim 1, wherein the source region has a first width at a first position above the substrate, the source region has a second width at a second position above the substrate, the second position being a different distance from the substrate than the first position, and the first width is greater than the second width.

6. The device of claim 5, wherein the first width of the source is greater than a maximum width of the first nanowire.

7. The device of claim 1, further comprising an isolation region layer over a first portion of the substrate, wherein a second portion of the substrate extends up past a bottom surface of the isolation region layer.

8. The device of claim 7, wherein the second portion of the substrate does not extend up to a top surface of the isolation region layer.

9. The device of claim 7, wherein at least portions of the first and second nanowires are directly above the second portion of the substrate, but are not in direct contact with the second portion of the substrate.

10. The device of claim 1, wherein the drain region has a side wall, the side wall of the drain region is a <

111>

facet.

11. A semiconductor device, comprising:

a semiconductor substrate comprising a first semiconductor material, the semiconductor substrate having a top surface, wherein the first semiconductor material of the semiconductor substrate adjacent the top surface has a first lattice constant;

an epitaxial source region on the top surface of the semiconductor substrate, the epitaxial source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;

an epitaxial drain region on the top surface of the semiconductor substrate, the epitaxial drain region comprising the second material with the second lattice constant different than the first lattice constant, the epitaxial drain region being spaced apart from the epitaxial source region;

a first channel material region above the substrate, at least a portion of the first channel material region being between the epitaxial source region and the epitaxial drain region, the first channel material region being coupled to the epitaxial source region and the epitaxial drain region, the first channel material region having a length measured along a first direction that extends from the epitaxial source region to the epitaxial drain region, the length of the first channel material region being great enough to span at least most of a distance between the epitaxial source region and the epitaxial drain region, the first channel material region having a height measured along a second direction that extends up from the substrate, the first channel material region having a width measured along a third direction substantially orthogonal to the first direction and the second direction, the first channel material region comprising a third material, the third material having a third lattice constant, the first channel material region having a first channel region;

a second channel material region above the substrate, at least a portion of the second channel material region being directly above the first channel material region and not in direct contact with the first channel material region, at least a portion of the second channel material region being between the epitaxial source region and the epitaxial drain region, the second channel material region being coupled to the epitaxial source region and the epitaxial drain region, the second channel material region having a length measured along the first direction, the length of the second channel material region being great enough to span at least most of a distance between the epitaxial source region and the epitaxial drain region, the second channel material region having a height measured along the second direction, the second channel material region having a width measured along the third direction, the second channel material region comprising the third material, the second channel material region having a second channel region;

a first gate dielectric layer around the first channel region of the first channel material region, the first gate dielectric layer surrounding the first channel region in a first cross section taken normal to a line extending from the source region to the drain region, the first gate dielectric layer not completely surrounding the first channel region in a second cross section taken through the first channel material region and parallel with a top surface of the substrate, the first gate dielectric layer comprising a first gate dielectric material;

a second gate dielectric layer around the second channel region of the second channel material region, the second gate dielectric layer surrounding the second channel region in a first cross section taken normal to a line extending from the source region to the drain region, the second gate dielectric layer not completely surrounding the second channel region in a second cross section taken through the second channel material region and parallel with a top surface of the substrate, the second gate dielectric layer comprising the first gate dielectric material; and

a gate electrode material around the first channel region of the first channel material region and around the second channel region of the second channel material region, the gate electrode material being separated from the first channel region of the first channel material region by the first gate dielectric layer, the gate electrode material being separated from the second channel region of the second channel material region by the second gate dielectric layer.

12. The device of claim 11, wherein the second lattice constant is larger than the first lattice constant.

13. The device of claim 11, wherein the third lattice constant is different than the first lattice constant.

14. The device of claim 11, wherein the third lattice constant is substantially the same as the second lattice constant.

15. The device of claim 11, wherein the third material is the same as the second material.

16. The device of claim 11, wherein the epitaxial source region and the epitaxial drain region both have side walls that are angled.

17. The device of claim 11, wherein the epitaxial source region has a first width at a first position above the substrate, the epitaxial source region has a second width at a second position above the substrate, the second position being a different distance from the substrate than the first position, and the first width is greater than the second width, the first width and the second width both being measured along the third direction.

18. The device of claim 11, further comprising:

a third channel material region above the substrate, at least a portion of the third channel material region being directly above the first channel material region and directly above the second channel material region and not in direct contact with the first channel material region or the second channel material region, at least a portion of the third channel material region being between the epitaxial source region and the epitaxial drain region, the third channel material region being coupled to the epitaxial source region and the epitaxial drain region, the third channel material region having a length measured along the first direction, the length of the third channel material region being great enough to span at least most of a distance between the epitaxial source region and the epitaxial drain region, the third channel material region having a height measured along the second direction, the third channel material region having a width measured along the third direction, the third channel material region comprising the third material, the third channel material region having a third channel region.

19. The device of claim 11, wherein the first channel material region and the second channel material region are both nanowires.