Display substrate and method of manufacturing a display substrate

• US 9,252,284 B2
• Filed: 02/18/2014
• Issued: 02/02/2016
• Est. Priority Date: 09/02/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Khang, Yoon-Ho, Kang, Su-Hyoung, Kim, Dong-Jo, Lee, Ji-Seon, Cha, Myoung-Geun, Ji, Deuk-Myung, Lee, Jong-Chan
• Primary Examiner(s): MOORE, WHITNEY
• Application Number:
  US14/182,989
• Publication Number:
  US 20150060843A1
• Time in Patent Office: 714 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.

Claims

1. A display substrate, comprising:

a substrate;

a gate electrode disposed on the substrate;

an active pattern comprising an oxide semiconductor, the active pattern comprising a first region, a second region, and a third region, the first region of the active pattern overlapping the gate electrode and having an electrical conductivity smaller than those of the second region and the third region;

a first insulation layer pattern and a second insulation layer pattern disposed on the first region of the active pattern, the first insulation layer pattern and the second insulation layer pattern overlapping the gate electrode; and

a third insulation layer covering the active pattern, the first insulation layer pattern, and the second insulation layer pattern, contacting the second region and the third region and being separated from the first region, and the third insulation layer comprising at least one of silicon nitride and silicon oxy-nitride,

wherein either the first insulation layer pattern or the second insulation layer pattern comprises aluminum oxide, and

wherein each of the first insulation layer pattern and the second insulation layer pattern has a width substantially the same as a width of the gate electrode.

2. The display substrate of claim 1, wherein the first region of the active pattern has a width substantially the same as the width of the first insulation layer pattern.

3. The display substrate of claim 1, wherein the second region and the third region of the active pattern are self-aligned to not overlap the gate electrode.

4. The display substrate of claim 1, wherein the first insulation layer pattern and the second insulation layer pattern reduce a diffusion or a doping of the impurities from the third insulation layer into the first region of the active pattern.

5. The display substrate of claim 1, further comprising a fourth insulation layer pattern disposed on the second insulation layer pattern.

6. The display substrate of claim 1, further comprising a gate insulation layer disposed between the gate electrode and the active pattern.

wherein the active pattern comprises at least one of amorphous zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).