Display device and electronic appliance

• US 9,252,287 B2
• Filed: 03/06/2015
• Issued: 02/02/2016
• Est. Priority Date: 09/13/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US14/640,410
• Publication Number:
  US 20150243794A1
• Time in Patent Office: 333 Days
• Field of Search: 257/43, 257/59, 257/71, 257/72
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A display device with low manufacturing cost, with low power consumption, capable of being formed over a large substrate, with a high aperture ratio of a pixel, and with high reliability is provided. The display device includes a transistor electrically connected to a light-transmitting pixel electrode and a capacitor. The transistor includes a gate electrode, a gate insulating film over the gate electrode, and a first multilayer film including an oxide semiconductor over the gate insulating film. The capacitor includes the pixel electrode and a conductive electrode formed of a second multilayer film which overlaps with the pixel electrode with a predetermined distance therebetween, and has the same layer structure as the first multilayer film. A channel formation region of the transistor is at least one layer, which is not in contact with the gate insulating film, of the first multilayer film.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a first oxide layer on an insulating surface, a second oxide layer over the first oxide layer, and a third oxide layer over the second oxide layer; and

a source electrode and a drain electrode electrically connected to the first oxide layer, the second oxide layer, and the third oxide layer;

a silicon insulating layer containing excess oxygen over and in contact with the third oxide layer, the source electrode, and the drain electrode;

a nitride insulating layer over the silicon insulating layer; and

a capacitor comprising;

a first electrode in contact with the silicon insulating layer; and

the nitride insulating layer overlapping the first electrode,

wherein the first oxide layer, the second oxide layer, the third oxide layer, and the first electrode comprise a same material, and

wherein the second oxide layer comprises a channel formation region of the transistor.

4. The semiconductor device according to claim 1, wherein the silicon insulating layer has a stacked-layer structure.

5. The semiconductor device according to claim 1, wherein the first electrode is over and in contact with the silicon insulating layer.

6. The semiconductor device according to claim 1, wherein the first electrode has a stacked-layer structure.

7. The semiconductor device according to claim 1, wherein the first electrode contains an impurity imparting n-type conductivity at a concentration higher than the first oxide layer, the second oxide layer, or the third oxide layer contains.

8. The semiconductor device according to claim 1, wherein the first oxide layer, the second oxide layer, and the third oxide layer are oxide semiconductor layers.

2. A semiconductor device comprising:

a transistor comprising;

a first oxide layer on an insulating surface, a second oxide layer over the first oxide layer, and a third oxide layer over the second oxide layer; and

a source electrode and a drain electrode electrically connected to the first oxide layer, the second oxide layer, and the third oxide layer;

a silicon insulating layer containing excess oxygen over and in contact with the third oxide layer, the source electrode, and the drain electrode;

a nitride insulating layer over the silicon insulating layer; and

a capacitor comprising;

a first electrode in contact with the silicon insulating layer; and

the nitride insulating layer overlapping the first electrode,

wherein the first oxide layer, the second oxide layer, the third oxide layer, and the first electrode comprise indium, gallium, and zinc, and

wherein the second oxide layer comprises a channel formation region of the transistor.

9. The semiconductor device according to claim 2, wherein the silicon insulating layer has a stacked-layer structure.

10. The semiconductor device according to claim 2, wherein the first electrode is over and in contact with the silicon insulating layer.

11. The semiconductor device according to claim 2, wherein the first electrode has a stacked-layer structure.

12. The semiconductor device according to claim 2, wherein the first electrode contains an impurity imparting n-type conductivity at a concentration higher than the first oxide layer, the second oxide layer, or the third oxide layer contains.

13. The semiconductor device according to claim 2, wherein the first oxide layer, the second oxide layer, and the third oxide layer are oxide semiconductor layers.

3. A semiconductor device comprising:

a transistor comprising;

a gate electrode;

a gate insulating film over the gate electrode;

a first oxide layer on an insulating surface, a second oxide layer over the first oxide layer, and a third oxide layer over the second oxide layer; and

a source electrode and a drain electrode electrically connected to the first oxide layer, the second oxide layer, and the third oxide layer;

a silicon insulating layer containing excess oxygen over and in contact with the third oxide layer, the source electrode, and the drain electrode;

a nitride insulating layer over the silicon insulating layer; and

a capacitor comprising;

a first electrode in contact with the silicon insulating layer; and

the nitride insulating layer overlapping the first electrode,

wherein the first oxide layer, the second oxide layer, the third oxide layer, and the first electrode comprise indium, gallium, and zinc, and

wherein the second oxide layer comprises a channel formation region of the transistor.

14. The semiconductor device according to claim 3, wherein the silicon insulating layer has a stacked-layer structure.

15. The semiconductor device according to claim 3, wherein the first electrode is over and in contact with the silicon insulating layer.

16. The semiconductor device according to claim 3, wherein the first electrode has a stacked-layer structure.

17. The semiconductor device according to claim 3, wherein the first electrode contains an impurity imparting n-type conductivity at a concentration higher than the first oxide layer, the second oxide layer, or the third oxide layer contains.

18. The semiconductor device according to claim 3, wherein the first oxide layer, the second oxide layer, and the third oxide layer are oxide semiconductor layers.