Three-dimensional gallium nitride (GaN) pillar structure light emitting diode (LED)

• US 9,252,328 B2
• Filed: 03/27/2015
• Issued: 02/02/2016
• Est. Priority Date: 12/27/2011
• Status: Active Grant

• Current Assignee: Elux Inc.
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Crowder, Mark Albert, Zhan, Changqing, Schuele, Paul J.
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Fan, Bo
• Application Number:
  US14/671,793
• Publication Number:
  US 20150221827A1
• Time in Patent Office: 312 Days
• Field of Search: 257/13, 438/34
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/10156 at the periphery
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2933/0008 Processes
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/18 within the light emitting region
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01L 33/42 : Transparent materials

Abstract

A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Claims

1. A light emitting diode (LED) with three-dimensional gallium nitride (GaN) pillar structures having planar surfaces, the LED comprising:

a substrate with a top surface having a plurality of first electrode digits formed in a first metal layer, and a plurality of opposing second electrode digits formed in a second metal layer;

a plurality of GaN pillar structures, each GaN pillar structure bridging a gap between a first electrode digit and a corresponding second electrode digit;

each GaN pillar structure comprising;

an n-doped GaN (n-GaN) pillar having a first end overlying a corresponding first electrode digit, a second end connected to a corresponding second electrode digit, with at least one of the ends formed in a c-plane, and planar sidewalls perpendicular to the c-plane, formed in a plane selected from a group consisting of an m-plane and a-plane family;

a multiple quantum well (NNW) layer overlying the n-GaN pillar sidewalls and the GaN pillar first end; and

,

a layer of p-doped GaN (p-GaN) overlying the MQW layer.

2. The LED of claim 1 wherein the n-doped GaN pillars have a shape selected from a group consisting of hexagonal and triangular.

3. The LED of claim 1 further comprising:

a Ni layer overlying the p-GaN layer of each GaN pillar structure;

a transparent conductor overlying the Ni layer, wherein the combination of the Ni layer and transparent conductor electrically connect the p-GaN layer of each GaN pillar structure to a corresponding first electrode digit; and

,

a metal interconnect interposed between each exposed n-GaN pillar second end and the underlying second electrode digit.

14. The LED of claim 3 wherein the transparent conductor is a material selected from a group consisting of indium tin oxide (ITO), zinc oxide, carbon nanotubes (CNTs), and graphene.

15. The LED of claim 1 wherein each n-GaN pillar second end comprises an exposed n-GaN core corrected to a corresponding second electrode digit.

16. The LED of claim 1 further comprising;

a metal interconnect overlying the first metal layer;

a conformally coated Ni layer; and

,

a transparent conductor overlying the Ni layer, wherein the combination of the Ni layer and transparent conductor electrically connect the p-GaN layer of each GaN pillar structure to a corresponding second electrode digit.

17. The LED of claim 1 wherein the LEDs are connected in series.

18. The LED of claim 1 wherein the LEDs are connected in parallel.

19. The LED of claim 1 wherein a first plurality of parallel-connected LEDs are connected in series with a second plurality of parallel-connected LEDs.

4. A method for fabricating a light emitting diode (LED) using three-dimensional gallium (GaN) pillar structures with planar surfaces, the method comprising:

depositing the plurality of GaN pillar structures on a first substrate, having a first end, a second end, with at least one of the ends formed in a c-plane, and planar sidewalls perpendicular to the c-plane and formed in an a-plane family, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate;

connecting a first end of each GaN pillar structure to a first metal layer to form a first electrode;

etching a second end of each GaN pillar structure to expose the n-GaN pillar second end; and

,

subsequent to etching the second end of each GaN pillar structure, connecting the second end of each GaN pillar structure to a second metal layer to form a second electrode.

5. The method of claim 4 wherein depositing the GaN pillar structures includes depositing GaN pillar structures with pillar cores having a shape selected from a group consisting of hexagonal and triangular.

6. The method of claim 4 further comprising:

providing a first substrate top surface with a plurality of first electrode digits and a plurality of opposing second electrode digits;

wherein depositing the plurality of GaN pillar structures on the first substrate includes;

suspending the GaN pillar structures in an ink solution;

flowing the ink solution over the first substrate top surface;

creating an alternating current (AC) electric field with a first field strength between each first electrode digit and corresponding second electrode digit; and

,

in response to the electric field, bridging a gap between each first electrode digit and corresponding second electrode digit with a GaN pillar structure.

7. The method of claim 6 wherein depositing the plurality of GaN pillar structures includes:

subsequent to bridging the gap between first and second electrode digits with the GaN pillar structure, increasing the electric field strength to capture the GaN pillar structures;

flowing a solvent over the first substrate top surface; and

,

in response to the solvent flow, removing GaN pillar structures not captured by the electric field.

8. The method of claim 4 wherein connecting the first end of each GaN pillar structure to a first metal layer includes:

conformally depositing a Ni layer overlying the first substrate top surface and GaN pillar structures; and

,

conformally depositing a transparent conductor overlying the Ni layer.

9. The method of claim 8 wherein etching the second end of each GaN pillar structure to expose the n-GaN second end includes, prior to etching the second end of each GaN pillar structure, etching to remove the transparent conductor and Ni layers overlying the second end of each GaN pillar structure;

and,

wherein connecting the second end of each GaN pillar structure to the second metal layer includes forming a metal interconnect layer interposed between the exposed n-GaN and the second metal layer.

10. The method of claim 8 wherein connecting the first end of each GaN pillar structure to a first metal layer includes forming a metal interconnect layer over the first metal layer, prior to depositing the Ni layer.

11. The method of claim 8 wherein connecting the first end of each GaN pillar structure to a first metal layer includes forming a metal interconnect layer over the first metal layer, subsequent to depositing the transparent conductor.

12. The method of claim 8 wherein the transparent conductor is a material selected from a group consisting of indium tin oxide (ITO), zinc oxide, carbon nanotubes (CNTs), and graphene.

13. The method of claim 4 wherein etching a second end of each GaN pillar structure to expose the n-GaN pillar second end includes using a Cl₂ based reactive ion etch (RIE).