High voltage driver using medium voltage devices
First Claim
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1. A voltage drive circuit, comprising:
- a first plurality of transistors connected in series between a first source node and an output node;
a plurality of voltage sources configured to provide a voltage to at least one of the first plurality of transistors; and
a plurality of capacitors coupled across gates of the first plurality of transistors, each capacitor configured to store charges associated with changes at gates of the transistors, wherein the plurality of capacitors have capacitances selected to synchronize voltage changes at the first plurality of transistors,wherein the voltage drive circuit is configured to transition from a first steady state that provides a first voltage to a second steady state that provides a second voltage;
wherein the plurality of capacitors are configured to store charges while transitioning from the first steady state to the second steady state; and
wherein a difference between the first and second voltages is greater than a breakdown voltage of each of the first plurality of transistors.
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Abstract
A voltage drive circuit is constructed by stacking NMOS and PMOS transistors to provide high voltage levels with an output voltage swing greater than the breakdown voltage of the individual transistors used to build the voltage drive circuit. The voltage drive circuit may include a series stack of capacitors connected between gates of the stacked PMOS and NMOS transistors. The capacitive loading causes the gate signals to change more synchronously. Errors in timing for these gate signals, which would otherwise result in damage from exceeding the breakdown voltage across a pair of terminals of one of the NMOS and PMOS transistors, are mollified.
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Citations
19 Claims
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1. A voltage drive circuit, comprising:
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a first plurality of transistors connected in series between a first source node and an output node; a plurality of voltage sources configured to provide a voltage to at least one of the first plurality of transistors; and a plurality of capacitors coupled across gates of the first plurality of transistors, each capacitor configured to store charges associated with changes at gates of the transistors, wherein the plurality of capacitors have capacitances selected to synchronize voltage changes at the first plurality of transistors, wherein the voltage drive circuit is configured to transition from a first steady state that provides a first voltage to a second steady state that provides a second voltage; wherein the plurality of capacitors are configured to store charges while transitioning from the first steady state to the second steady state; and wherein a difference between the first and second voltages is greater than a breakdown voltage of each of the first plurality of transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A display device, comprising:
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voltage drive circuitry configured to provide a first voltage, the voltage drive circuitry comprising; a first plurality of transistors connected in series between a first source node and an output node; a plurality of voltage sources configured to provide a voltage to at least one of the first plurality of transistors, wherein each voltage source is configured to switch and maintain a voltage at a gate of at least one of the first plurality of transistors; a plurality of capacitors coupled across gates of the first plurality of transistors, each capacitor configured to store charges associated with changes at gates of the transistors, wherein the plurality of capacitors have capacitances selected to synchronize voltage changes at the first plurality of transistors; and at least one weak level shifter connected to at least one of the plurality of capacitors and configured to hold the connected capacitor from discharging; and a processing system coupled to the voltage drive circuitry and configured to transmit a first logic signal to the voltage drive circuitry corresponding to the first voltage. - View Dependent Claims (9, 10, 11, 12)
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13. A method for providing a high power output, the method comprising:
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applying a first source signal to a first source node of a first plurality of transistors connected in series; and charging a first plurality of capacitors coupled between gates of adjacent transistors of the first plurality of transistors connected in series at a rate operable to synchronize a change in state of the first plurality of transistors, wherein the change in state of the first plurality of transistors comprises a change from a first steady state providing a first voltage to a second steady state providing a second voltage, wherein the first plurality of capacitors are configured to store charges while transitioning from the first steady state to the second steady state; and wherein a difference between the first and second voltages is greater than a breakdown voltage of each of the first plurality of transistors. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification