Universal synchronization engine based on probabilistic methods for guarantee of lock in multiformat audio systems

• US 9,252,900 B2
• Filed: 03/14/2013
• Issued: 02/02/2016
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Malikie Innovations Limited (Key Patent Innovations Limited)
• Original Assignee: Blackberry Limited
• Inventors: Poulsen, Jens Kristian
• Primary Examiner(s): Acolatse, Kodzovi
• Application Number:
  US13/803,393
• Publication Number:
  US 20130322462A1
• Time in Patent Office: 1,055 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/3625 using a time dependent access
• CPC Class Codes: H04J 3/06 Synchronising arrangements for television systems H04N5/04; bit-synchronisation H04L7/00
• CPC Class Codes: H04L 1/1607 Details of the supervisory signal
• CPC Class Codes: H04L 2001/0094 Bus
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

Various embodiments are described herein related to techniques for synchronizing a slave device to a master device that communicates using a unified bus communication protocol or some aspect thereof. In one example, the method may comprise assuming a first mode of operation for the unified bus communication protocol; searching for a synchronization pattern at one or more locations in transmitted data according to the first mode of operation; obtaining synchronization when the located synchronization pattern is verified according to at least one synchronization rule for the mode of operation; and if synchronization is not obtained based on the assumed first mode of operation, a second mode of operation for the unified bus communication protocol is assumed and the searching and obtaining acts are carried out on the transmitted data according to the second mode of operation.

Claims

1. A method of synchronizing a slave device to a master device that communicates using a unified bus communication protocol, the unified bus communication protocol having a first mode of operation and a second mode of operation, the method comprising:

searching, according to the first mode of operation, for a first synchronization pattern, the first mode of operation having a first constant gap in between transmitted synchronization bits, the first synchronization pattern comprising a first constant sync portion and a first dynamic sync portion, the searching for the first synchronization pattern comprising searching for the first constant sync portion;

obtaining synchronization when the first synchronization pattern is located and the located first synchronization pattern is verified according to at least one synchronization rule for the first mode of operation; and

if synchronization is not obtained;

searching, according to the second mode of operation, for a second synchronization pattern, the second mode of operation having a second constant gap in between transmitted synchronization bits different from the first constant gap, the second synchronization pattern comprising a second constant sync portion and a second dynamic sync portion, the searching for the second synchronization pattern comprising searching for the second constant sync portion; and

obtaining synchronization when the second synchronization pattern is located and the located second synchronization pattern is verified according to at least one synchronization rule for the second mode of operation,

wherein the first constant sync portion is different than the second constant sync portion.

2. The method of claim 1, wherein the dynamic sync portion of the located synchronization pattern is generated by a deterministic method such that the dynamic sync portions of two consecutive synchronization patterns are different.

3. The method of claim 2, wherein the searching and obtaining acts comprise reading a current dynamic sync portion associated with a constant sync portion that is located, the at least one synchronization rule comprises calculating an expected dynamic sync portion based on the deterministic method and the current dynamic sync portion, locating a next constant sync portion and comparing a dynamic sync portion associated with the next constant sync portion with the expected dynamic sync portion to reduce the chance of false synchronization.

4. The method of claim 3, wherein the at least one synchronization rule comprises repeating the calculating, locating and comparing acts one or more times to further reduce the chance of false synchronization.

5. The method of claim 3, wherein the method further comprises maintaining a current located constant sync portion regardless of not finding a match between an expected dynamic sync portion and an actual dynamic sync portion until the searching exceeds a maximum frame length at which point the current located constant sync portion is discarded and an ensuing constant sync portion is used as the current located constant sync portion and the search for the match is continued.

6. The method of claim 1, wherein at least one of the first mode and the second mode is a word mode of operation, the word mode of operation having a constant gap of zero bits in between transmitted synchronization bits, and the searching, according to the word mode of operation, for the first synchronization pattern or for the second synchronization pattern is performed on the transmitted data for various starting time slot positions up to and including a maximum frame length unless the respective synchronization pattern has been located earlier.

7. The method of claim 1, wherein at least one of the first mode and the second mode is a bitstream mode of operation, the bitstream mode of operation having a constant gap of a positive integer number of bits in between transmitted synchronization bits, and the searching, according to the bitstream mode of operation, for the first synchronization pattern or for the second synchronization pattern is performed on the transmitted data for various starting time slot positions up to and including a maximum frame length and this is repeated for a maximum number of frame channels unless the respective synchronization pattern has been located earlier.

8. The method of claim 1, further comprising, once the synchronization pattern has been located, searching for next occurrence of the located synchronization pattern in the transmitted data in order to determine a frame length that is being used by the unified bus communication protocol.

9. The method of claim 1, wherein if the slave device falls out of synchronization, the slave device assumes a frame length and a frame format determined during a previous successful synchronization attempt and attempts to regain synchronization.

10. An electronic device that communicates according to a unified bus communication protocol, the unified bus communication protocol having a first mode of operation and a second mode of operation, the electronic device comprising:

an interface for sending and receiving signals; and

a mux and sync engine coupled to the interface, the mux and sync engine being configured to synchronize the electronic device, acting as a slave device, with another electronic device acting as a master device, by;

searching, according to the first mode of operation, for a first synchronization pattern, the first mode of operation having a first constant gap in between transmitted synchronization bits, the first synchronization pattern comprising a first constant sync portion and a first dynamic sync portion, the searching for the first synchronization pattern comprising searching for the first constant sync portion;

obtaining synchronization when the first synchronization pattern is located and the located first synchronization pattern is verified according to at least one synchronization rule for the first mode of operation; and

if synchronization is not obtained;

searching, according to the second mode of operation, for a second synchronization pattern, the second mode of operation having a second constant gap in between transmitted synchronization bits different from the first constant gap, the second synchronization pattern comprising a second constant sync portion and a second dynamic sync portion, the searching for the second synchronization pattern comprising searching for the second constant sync portion; and

obtaining synchronization when the second synchronization pattern is located and the located second synchronization pattern is verified according to at least one synchronization rule for the second mode of operation,

wherein the first constant sync portion is different than the second constant sync portion.

11. The electronic device of claim 10, wherein the dynamic sync portion of the located synchronization pattern is generated by a deterministic method such that the dynamic sync portions of two consecutive synchronization patterns are different.

12. The electronic device of claim 11, wherein the searching and obtaining acts comprise reading a current dynamic sync portion associated with a constant sync portion that is located, the at least one synchronization rule comprises calculating an expected dynamic sync portion based on the deterministic method and the current dynamic sync portion, locating a next constant sync portion and comparing a dynamic sync portion associated with the next constant sync portion with the expected dynamic sync portion to reduce the chance of false synchronization.

13. The electronic device of claim 12, wherein the at least one synchronization rule comprises repeating the calculating, locating and comparing acts one or more times to further reduce the chance of false synchronization.

14. The electronic device of claim 12, wherein the method further comprises maintaining a current located constant sync portion regardless of not finding a match between an expected dynamic sync portion and an actual dynamic sync portion until the searching exceeds a maximum frame length at which point the current located constant sync portion is discarded and an ensuing constant sync portion is used as the current located constant sync portion and the search for the match is continued.

15. The electronic device of claim 10, wherein at least one of the first mode and the second mode is a word mode of operation, the word mode of operation having a constant gap of zero bits in between transmitted synchronization bits, and the searching, according to the word mode of operation, for the first synchronization pattern or for the second synchronization pattern is performed on the transmitted data for various starting time slot positions up to and including a maximum frame length unless the respective synchronization pattern has been located earlier.

16. The electronic device of claim 10, wherein at least one of the first mode and the second mode is a bitstream mode of operation, the bitstream mode of operation having a constant gap of a positive integer number of bits in between transmitted synchronization bits, and the searching, according to the bitstream mode of operation, for the first synchronization pattern or for the second synchronization pattern is performed on the transmitted data for various starting time slot positions up to and including a maximum frame length and this is repeated for a maximum number of frame channels unless the respective synchronization pattern has been located earlier.

17. The electronic device of claim 10, the mux and sync engine being further configured to search, once the synchronization pattern has been located, for a next occurrence of the located synchronization pattern in the transmitted data in order to determine a frame length that is being used by the unified bus communication protocol.

18. The electronic device of claim 10, wherein if the slave device falls out of synchronization, the slave device assumes a frame length and a frame format determined during previous a previous successful synchronization attempt and attempts to regain synchronization.

19. A non-transitory computer readable medium comprising a plurality of instructions executable on a microprocessor of a slave device for adapting the microprocessor to implement a method of synchronizing the slave device to a master device that communicates using a unified bus communication protocol, the unified bus communication protocol having a first mode of operation and a second mode of operation, the method comprising:

searching, according to the first mode of operation, for a first synchronization pattern at one or more locations in transmitted data, the first mode of operation having a first constant gap in between transmitted synchronization bits, the first synchronization pattern comprising a first constant sync portion and a first dynamic sync portion, the searching for the first synchronization pattern comprising searching for the first constant sync portion;

obtaining synchronization when the first synchronization pattern is located and the located first synchronization pattern is verified according to at least one synchronization rule for the first mode of operation; and

if synchronization is not obtained;

searching, according to the second mode of operation, for a second synchronization pattern at one or more locations in the transmitted data, the second mode of operation having a second constant gap in between transmitted synchronization bits different from the first constant gap, the second synchronization pattern comprising a second constant sync portion and a second dynamic sync portion, the searching for the second synchronization pattern comprising searching for the second constant sync portion; and

obtaining synchronization when the second synchronization pattern is located and the located second synchronization pattern is verified according to at least one synchronization rule for the second mode of operation,

wherein the first constant sync portion is different than the second constant sync portion.