Electronic apparatus having IC temperature control
First Claim
1. A method for controlling heating of a circuit, comprising:
- determining a current temperature of the circuit in a normal operational mode;
determining a desired temperature of the circuit;
writing a first address to a mode register of the circuit, the address comprising a heat enable bit configured to enable a heat function of the circuit; and
when the current temperature is substantially equal to or greater than the desired temperature, writing a second address to the mode register, the second address comprising a heat disable bit configured to disable the heat function.
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Accused Products
Abstract
The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.
51 Citations
20 Claims
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1. A method for controlling heating of a circuit, comprising:
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determining a current temperature of the circuit in a normal operational mode; determining a desired temperature of the circuit; writing a first address to a mode register of the circuit, the address comprising a heat enable bit configured to enable a heat function of the circuit; and when the current temperature is substantially equal to or greater than the desired temperature, writing a second address to the mode register, the second address comprising a heat disable bit configured to disable the heat function. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device comprising:
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a memory array on a substrate; a heater circuit on the substrate; and a mode register on the substrate, wherein the mode register is configured to control the heater circuit in response to an address written to the memory device. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification