Handling interrupt actions for inter-thread communication

• US 9,256,461 B2
• Filed: 09/18/2013
• Issued: 02/09/2016
• Est. Priority Date: 09/18/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Declercq, Andrew J., Gheith, Ahmed, Kumar, Aditya
• Primary Examiner(s): Al Kawsar, Abdullah
• Assistant Examiner(s): Zhao, Bing
• Application Number:
  US14/030,366
• Publication Number:
  US 20150082324A1
• Time in Patent Office: 874 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure.

Claims

1. A computer program product comprising a non-transitory computer recordable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

provide in association with a first processor thread, a thread action data structure comprising a non-blocking synchronization data structure and an internal list data structure of pending interrupts, wherein the thread action data structure associated with the first processor thread receives interrupts from other processor threads in the computing device;

receive a post of an interrupt action from a second processor thread to the thread action data structure associated with the first processor thread, wherein the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure;

move the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor read, wherein, responsive to receiving a post of a new interrupt action while the interrupt action is being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts, the computer readable program further causes the computing device to;

delay the posting of the new interrupt action to the non-blocking synchronization data structure until after the interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts;

responsive to the interrupt action being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts, add the new interrupt action to the non-blocking synchronization data structure of the thread action data structure; and

update a atomic reference to a head of the non-blocking synchronization data structure in response adding the new interrupt action from the second processor thread to the thread action data structure associated with the first processor thread, wherein the atomic reference to the head of the non-blocking synchronization data structure points to the new interrupt action in the non-blocking synchronization data structure; and

process the internal list data structure of pending interrupts to thereby handle interrupt actions moved to the internal list data structure.

2. The computer program product of claim 1, wherein the computer readable program to move the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread further causes the computing device to:

advance an atomic reference to a next most recently posted interrupt action in the non-blocking synchronization data structure in response to moving the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread.

3. The computer program product of claim 1, wherein the computer readable program further causes the computing device to:

block posting of interrupt actions by other threads to the non-blocking synchronization data structure while the interrupt action is being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts.

4. The computer program product of claim 1, wherein the computer readable program further causes the computing device to:

update the atomic reference to the head of the non-blocking synchronization data structure in response to receiving the post of the interrupt action from the second processor thread to the thread action data structure associated with the first processor thread, wherein the atomic reference points to the interrupt action from the second processor thread in the non-blocking synchronization data structure.

5. The computer program product of claim 1, wherein the computer readable program further causes the computing device to:

periodically check the atomic reference to the head of the non-blocking synchronization data structure to determine whether there are any pending interrupt actions in the non-blocking synchronization data structure; and

responsive to determining that there are pending interrupt actions in the non-blocking synchronization data structure based on results of checking the atomic reference to the head, move the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread.

6. The computer program product of claim 1, wherein the computer readable program further causes the computing device to:

provide in association with all processor threads in the data processing system, a respective thread action data structure comprising a respective non-blocking synchronization data structure and a respective internal list data structure of pending interrupts.

7. An apparatus comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to;

provide in association with a first processor thread, a thread action data structure comprising a non-blocking synchronization data structure and an internal list data structure of pending interrupts, wherein the thread action data structure associated with the first processor thread receives interrupts from other processor threads in the computing device;

receive a post of an interrupt action from a second processor thread to the thread action data structure associated with the first processor thread, wherein the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure;

move the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread, wherein, responsive to receiving a post of a new interrupt action while the interrupt action is being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts, the instructions further cause the processor to;

delay the posting of the new interrupt action to the non-blocking synchronization data structure until after the interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts;

responsive to the interrupt action being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts, add the new interrupt action to the non-blocking synchronization data structure of the thread action data structure; and

update an atomic reference to a head of the non-blocking synchronization data structure in response adding the new interrupt action from the second processor thread to the thread action data structure associated with the first processor thread, wherein the atomic reference to the head of the non-blocking synchronization data structure points to the new interrupt action in the non-blocking synchronization data structure; and

process the internal list data structure of pending interrupts to thereby handle interrupt actions moved to the internal list data structure.

8. The apparatus of claim 7, wherein the instructions to move the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread further cause the processor to:

advance an atomic reference to a next most recently posted interrupt action in the non-blocking synchronization data structure in response to moving the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread.

9. The apparatus of claim 7, wherein the instructions further cause the processor to:

block posting of interrupt actions by other threads to the non-blocking synchronization data structure while the interrupt action is being moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts.

10. The apparatus of claim 7, wherein the instructions further cause the processor to:

update the atomic reference to the head of the non-blocking synchronization data structure in response to receiving the post of the interrupt action from the second processor thread to the thread action data structure associated with the first processor thread, wherein the atomic reference points to the interrupt action from the second processor thread in the non-blocking synchronization data structure.

11. The apparatus of claim 7, wherein the instructions further cause the processor to:

periodically check the atomic reference to the head of the non-blocking synchronization data structure to determine whether there are any pending interrupt actions in the non-blocking synchronization data structure; and

responsive to determining that there are pending interrupt actions in the non-blocking synchronization data structure based on results of checking the atomic reference to the head, move the interrupt action from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread.

12. The apparatus of claim 7, wherein the instructions further cause the processor to:

provide in association with all processor threads in the data processing system, a respective thread action data structure comprising a respective non-blocking synchronization data structure and a respective internal list data structure of pending interrupts.