Memory controller for selective rank or subrank access

• US 9,256,557 B2
• Filed: 12/02/2014
• Issued: 02/09/2016
• Est. Priority Date: 05/02/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): LI, ZHUO H
• Application Number:
  US14/558,517
• Publication Number:
  US 20150089163A1
• Time in Patent Office: 434 Days
• Field of Search: 711/4, 711/100, 711/103, 711111-112, 711114-115, 711147-150, 711/152, 711167-168, 710 20- 21, 710 36- 38, 710/200, 710/305, 710/309
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09227 Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Claims

1. A memory controller, comprising:

at least one transaction queue to direct memory commands to first and second memory devices as a unified rank in a first mode, and to direct memory commands to the first and second memory devices as respective subranks in a second mode;

a command bus interface to direct the memory commands to the memory devices via a shared command bus;

a data bus interface having a width with a first portion of the width to be coupled to the first memory device but not the second memory device and a second portion of the width to be coupled to the second memory device but not the first memory device; and

circuitry to associate data exchanged via both of the first portion and the second portion with each of the memory commands in the first mode, and to associate data exchanged via an exclusive one of the first portion and the second portion with respective memory commands in the second mode.

2. The memory controller of claim 1, further comprising a command path multiplexer to, in the first mode, direct commands from only one of a first transaction queue or a second transaction queue to the command bus interface and, in the second mode, to multiplex commands from the first transaction queue with commands from the second transaction queue, to the command bus interface.

3. The memory controller of claim 2, further comprising arbitration logic to enable arbitrated access to the shared command bus by the command queues to direct memory commands to the memory devices.

4. The memory controller of claim 1, where the at least one transaction queue comprises a first transaction queue and a second transaction queue and the memory controller is to direct in the second mode memory commands from the first transaction queue and the second transaction queue to respective ones of the first and second memory devices.

5. The memory controller of claim 1, where the memory controller is operable to change mode dynamically between the first mode and the second mode.

6. The memory controller of claim 1, where the memory controller is to configure at least one of the first or second memory devices in association with a change between the first mode and the second mode by command to at least one of the first memory device and the second memory device issued from, in the first mode, a first transaction queue of the at least one transaction queue, and in the second mode, a second transaction queue of the at least one transaction queue.

7. The memory controller of claim 1, where the memory controller is to configure at least one of the first or second memory devices in association with a change between the first mode and the second mode by command to at least one of the first memory device and the second memory device.

8. The memory controller of claim 1, where the memory controller is to sample a serial presence detect memory and is to responsively adopt the first mode or the second mode dependent on content of the serial presence detect memory.

9. The memory controller of claim 1, operable in a system where the first and second memory devices are part of a memory module, where the memory controller is to interact with the memory module and each memory device via the shared control path.

10. The memory controller of claim 9, operable in a system in which there are plural instances of the memory module, where:

the first portion couples the memory controller to a first memory device but not a second memory device for each memory module and the second portion couples the memory controller to the second memory device but not the first memory device for each memory module;

the memory controller is to in the first mode direct memory commands to the first and second memory devices of each memory module as a unified rank, and to associate data exchanged via the data bus interface with individual memory commands; and

the memory controller is to in the second mode direct memory commands to individual ones of the first and second memory devices for each memory module, and to associate data exchanged the first portion only and data exchanged via the second portion only with respective memory commands.

11. The memory controller of claim 1, where in the second mode, data exchanged via the first portion only is associated exclusively with commands in a first transaction queue and data exchanged via the second portion only is associated exclusively with commands in a second transaction queue.

12. The memory controller of claim 1, where:

the memory controller is to program information into at least one of the first memory device and the second memory device, where the information comprises at least one of a sampling latency to trigger sampling of the shared command bus, a chip select polarity to trigger sampling of the shared command bus, and a device ID to trigger sampling of the shared command bus; and

in the second mode, memory commands are to be sent to both the first memory device and the second memory device via the shared command bus, but are to be selectively sampled by each memory device according to the programmed information.

13. The memory controller of claim 1, where:

the memory controller further comprises a chip select output for each of the first memory device and the second memory device; and

the memory controller is to issue a chip select signal using the chip select outputs for the respective first and second memory devices, where the respective chip select signals are operated in lock-step in the first mode, and where the respective chip select signals are not operated in lock-step in the second mode.

14. The memory controller of claim 1, where:

the memory controller is operable to generate a mode select signal to define operating mode as either the first mode or the second mode; and

the memory controller is operable to generate a source select signal to route commands from a selective one of a first transaction queue or a second transaction queue to the shared command path.

15. The memory controller of claim 1, where the memory commands and the circuitry in the first mode effectuate memory access of a first granularity, and where the memory commands and the circuitry in the second mode effectuate memory access of a second granularity.

16. An apparatus, comprising:

at least one transaction queue to direct memory commands to first and second memory devices as a unified rank in a first mode, and to direct memory commands to the first and second memory devices as respective subranks in a second mode;

a command bus interface to direct the memory commands to the memory devices via a shared command bus;

a data bus interface having a width with a first portion of the width to be coupled to the first memory device but not the second memory device and a second portion of the width to be coupled to the second memory device but not the first memory device; and

circuitry to associate data exchanged via both of the first portion and the second portion with each of the memory commands in the first mode, and to associate data exchanged via an exclusive one of the first portion and the second portion with respective memory commands in the second mode.

17. The apparatus of claim 16, embodied as a memory controller, where:

the memory controller further comprises a chip select output for each of the first memory device and the second memory device; and

the respective chip select signals are operated in lock-step in the first mode, and where the respective chip select signals are not operated in lock-step in the second mode.

18. The apparatus of claim 16, where the memory commands and the circuitry in the first mode effectuate memory access of a first granularity, and where the memory commands and the circuitry in the second mode effectuate memory access of a second granularity.

19. The apparatus of claim 16, embodied as a memory system, where the apparatus also comprises the shared command bus, a data bus coupled to the data bus interface, and the first and second memory devices.

20. An apparatus, comprising:

at least one transaction queue to direct memory commands to first and second memory devices as a unified rank in a first mode, and to direct memory commands to the first and second memory devices as respective subranks in a second mode;

a command bus interface to direct the memory commands to the memory devices via a shared command bus;

a data bus interface having a width with a first portion of the width to be coupled to the first memory device but not the second memory device and a second portion of the width to be coupled to the second memory device but not the first memory device; and

means for associating data exchanged via both of the first portion and the second portion with each of the memory commands in the first mode, and for associating data exchanged via an exclusive one of the first portion and the second portion with respective memory commands in the second mode.