Dynamic thread status retrieval using inter-thread communication

• US 9,256,574 B2
• Filed: 03/11/2013
• Issued: 02/09/2016
• Est. Priority Date: 02/14/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kuesel, Jamie R., Kupferschmidt, Mark G., Schardt, Paul E., Shearer, Robert A.
• Primary Examiner(s): Partridge, William B
• Assistant Examiner(s): NGUYEN, WILLIAM V
• Application Number:
  US13/793,458
• Publication Number:
  US 20140229706A1
• Time in Patent Office: 1,065 Days
• Field of Search: 712/31, 712/34, 712/35
• US Class Current: 1/1
• CPC Class Codes: G06F 11/30 Monitoring
• CPC Class Codes: G06F 11/3031 where the computing system component is a motherboard or an expansion card
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 11/3072 where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting
• CPC Class Codes: G06F 11/3096 wherein the means or processing minimize the use of computing system or of computing system component resources, e.g. non-intrusive monitoring which minimizes the probe effect: sniffing, intercepting, indirectly deriving the monitored data from other directly available data
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

A circuit arrangement, method, and program product for dynamically providing a status of a hardware thread/hardware resource independent of the operation of the hardware thread/hardware resource using an inter-thread communication protocol. A master hardware thread may be configured to communicate status requests to associated slave hardware threads and/or hardware resources. Each slave hardware thread/hardware resource may be configured with hardware logic configured to automatically determine status information for the slave hardware thread/hardware resource and communicate a status response to the master hardware thread independent of the operation of the slave hardware thread/hardware resource.

Claims

1. A circuit arrangement comprising:

an on-chip network; and

a plurality of interconnected integrated processor blocks coupled to the on-chip network and arranged in a network on a chip (NOC) configuration, a first integrated processor block among the plurality of integrated processor blocks comprising;

a slave hardware thread;

an inbox coupled to the slave hardware thread and configured to receive a status request from a master hardware thread disposed in a different integrated processor block; and

status logic coupled to the inbox and configured to determine a status associated with the slave hardware thread and communicate a status response to the master hardware thread based at least in part on the status, wherein the status logic is configured to determine the status associated with the slave hardware thread without interrupting processing of the slave hardware thread;

wherein the inbox is configured to receive a configuration message from the master hardware thread, wherein the first integrated processor block is configured to process the configuration message to configure the status logic to automatically communicate a status response to the master hardware thread responsive to receiving a status request, wherein the master hardware thread is further configured to communicate the status request, and monitor the receipt of the status response to determine whether the status response was received within a predefined amount of time from communicating the status request.

2. The circuit arrangement of claim 1, wherein the first integrated processor block further comprises a status register configured to store status information for the slave hardware thread, and the status logic is configured to determine the status associated with the slave hardware thread by analyzing the status register.

3. The circuit arrangement of claim 1, wherein the status logic is configured to determine the status and communicate the status response concurrent with processing a software thread by the slave hardware thread.

4. The circuit arrangement of claim 1, wherein a second integrated processor block among the plurality of integrated processor blocks comprises:

a hardware thread configured as the master hardware thread and configured to receive the status response for the slave hardware thread, and store status information for the slave hardware thread to memory based at least in part on the received status response.

5. The circuit arrangement of claim 4, wherein the master hardware thread comprises thread status logic,

wherein the master hardware thread is configured to determine whether the status response is of a particular type by filtering the status response with a mask using the thread status logic prior to storing the status information for the slave hardware thread to memory, and

wherein the status information is stored to memory responsive to determining that the status response is of the particular type.

6. The circuit arrangement of claim 1, further comprising:

a hardware resource connected to the on-chip network;

an inbox coupled to the hardware resource and configured to receive a status request from the master hardware thread;

status logic coupled to the inbox of the hardware resource and configured to determine a status associated with the hardware resource and communicate a status response to the master hardware thread based at least in part on the status for the hardware resource, wherein the status logic of the hardware resource is configured to determine the status associated with the hardware resource independent of the operation of the hardware resource.

7. A program product comprising a non-transitory computer readable medium and logic definition program code resident on the computer readable medium and defining the circuit arrangement of claim 1.

8. A circuit arrangement comprising:

an on-chip network; and

a plurality of interconnected integrated processor blocks coupled to the on-chip network and arranged in a network on a chip (NOC) configuration, a first integrated processor block among the plurality of integrated processor blocks comprising;

a slave hardware thread;

an inbox coupled to the slave hardware thread and configured to receive a status request from a master hardware thread disposed in a different integrated processor block; and

status logic coupled to the inbox and configured to determine a status associated with the slave hardware thread and communicate a status response to the master hardware thread based at least in part on the status, wherein the status logic is configured to determine the status associated with the slave hardware thread without interrupting processing of the slave hardware thread;

wherein the inbox is configured to receive a configuration message from the master hardware thread, wherein the first integrated processor block is configured to process the configuration message to configure the status logic to automatically communicate a status response to the master hardware thread responsive to receiving a status request, wherein a second integrated processor block among the plurality of integrated processor blocks comprises a hardware thread configured as the master hardware thread and configured to receive the status response for the slave hardware thread, and store status information for the slave hardware thread to memory based at least in part on the received status response, wherein the master hardware thread comprises thread status logic, wherein the master hardware thread is configured to determine whether the status response is of a particular type by filtering the status response with a mask using the thread status logic prior to storing the status information for the slave hardware thread to memory, and wherein the status information is stored to memory responsive to determining that the status response is of the particular type.

9. The circuit arrangement of claim 8, wherein the first integrated processor block further comprises a status register configured to store status information for the slave hardware thread, and the status logic is configured to determine the status associated with the slave hardware thread by analyzing the status register.

10. The circuit arrangement of claim 8, wherein the status logic is configured to determine the status and communicate the status response concurrent with processing a software thread by the slave hardware thread.

11. The circuit arrangement of claim 8, further comprising:

a hardware resource connected to the on-chip network;

an inbox coupled to the hardware resource and configured to receive a status request from the master hardware thread;

status logic coupled to the inbox of the hardware resource and configured to determine a status associated with the hardware resource and communicate a status response to the master hardware thread based at least in part on the status for the hardware resource, wherein the status logic of the hardware resource is configured to determine the status associated with the hardware resource independent of the operation of the hardware resource.