Printed-circuit board supporting memory systems with multiple data-bus configurations

• US 9,257,151 B2
• Filed: 06/17/2014
• Issued: 02/09/2016
• Est. Priority Date: 02/28/2001
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Stark, Donald C., Ware, Frederick A., Tsern, Ely K., Hampel, Craig E.
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US14/306,304
• Publication Number:
  US 20140293671A1
• Time in Patent Office: 602 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1087 : Data input latches
• CPC Class Codes: G11C 8/06 : Address interface arrangements, e.g. address buffers
• CPC Class Codes: H05K 1/117 : Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 1/14 : Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 2201/09954 : More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
• CPC Class Codes: H05K 2201/10189 : Non-printed connector
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Claims

1. A printed-circuit board comprising:

a circuit mounting location for an integrated circuit comprising a memory controller;

a first module connector on the printed-circuit board, the first module connector to accept a first memory module having a first data bus width, the first data bus width specifying a first number of data bit lines;

a second module connector on the printed-circuit board, the second module connector to accept a second memory module having the first data bus width;

a first set of system data lines, fewer than the first number of data bit lines, extending directly to the first module connector from the circuit mounting location without connection to the second module connector;

a second set of system data lines, fewer than the first number of data bit lines, extending directly to the second module connector from the circuit mounting location without connection to the first module connector; and

a third set of system data lines, fewer than the first number of data bit lines, extending directly to the first module connector from the second module connector without connection to the circuit mounting location.

2. The printed-circuit board of claim 1, further comprising a continuity module inserted in the second module connector to connect each line in the second set of system data lines to a respective line in the third set of system data lines.

3. The printed-circuit board of claim 2, wherein the first number of data bit lines consists of the first and third sets of system data lines together comprise the first data bus width.

4. The printed-circuit board of claim 1, further comprising a third module connector on the printed-circuit board, the third module connector to accept an optional third memory module.

5. The printed-circuit board of claim 4, further comprising a fourth set of system data lines, less than the first data bus width, extending directly to the third module connector from the circuit mounting location without connection to the first module connector or the second module connector.

6. The printed-circuit board of claim 5, further comprising a fifth set of system data lines, less than the first data bus width, extending directly from the second module connector to the third module connector.

7. The printed-circuit board of claim 1, wherein the third set of system data lines includes the same number of signal lines as at least one of the first set of system data lines and the second set of system data lines.

8. The printed-circuit board of claim 1, further comprising address and control lines extending from the circuit mounting location to each of the first module connector and the second module connector.

9. A memory system comprising:

a printed-circuit board having a circuit mounting location for an integrated circuit, the integrated circuit including a memory controller;

a first module connector on the printed-circuit board, the first module connector to receive a memory module;

a second module connector on the printed-circuit board;

sets of system data lines, each set extending directly from the circuit mounting location to a different one of the first module connector and the second module connector, the sets of system data lines including;

a first set of system data lines extending from the circuit mounting location directly to the first module connector; and

a second set of system data lines extending from the circuit mounting location directly to the second module connector;

a third set of system data lines extending directly from the first module connector to second module connector; and

shorting conductors in the second module connector and interconnecting each data line of the second set of system data lines with a corresponding data line of the third set of system data lines.

10. The memory system of claim 9, further comprising a third module connector on the printed circuit board, the sets of system data lines further including a fourth set of system data lines extending from the circuit mounting location directly to the third module connector.

11. The memory system of claim 9, further comprising a memory module installed in the first module connector, the memory module having a first side connected to the circuit mounting location via the first set of system data lines and a second side connected to the circuit mounting location via the third set of system data lines, the shorting conductors, and the second set of system data lines.

12. The memory system of claim 9, wherein the shorting conductors extend through a shorting module.

13. The memory system of claim 9, wherein the first, second, and third sets of system data lines are point-to-point connections.

14. The memory system of claim 9, wherein the third set of system data lines includes the same number of data lines as at least one of the first and second sets of system data lines.

15. The memory system of claim 9, further comprising the memory module, the memory module supporting a first data-width configuration to communicate via both of the first and second sets of system data lines and a second data-width configuration to communicate via only one of the first and second sets of system data lines.