Setting a default read signal based on error correction

• US 9,257,203 B2
• Filed: 12/06/2012
• Issued: 02/09/2016
• Est. Priority Date: 12/06/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ratnam, Sampath K., Yanamanamanda, Satish K.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US13/706,851
• Publication Number:
  US 20140160845A1
• Time in Patent Office: 1,160 Days
• Field of Search: 365/185.09, 365/185.18, 365/185.33
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Apparatuses and methods related to setting a default read signal based on error correction include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections.

Claims

1. A method, comprising:

reading a page of user data from a group of memory cells with a first discrete read signal as part of a test operation during idle time of a memory apparatus;

error correcting, as part of the test operation during idle time of the memory apparatus, at least one codeword of the page of user data as read with the first discrete read signal;

reading the page of user data from the group of memory cells with a second discrete read signal different than the first discrete read signal as part of the test operation during idle time of the memory apparatus;

error correcting, as part of the test operation during idle time of the memory apparatus, at least one codeword of the page of user data as read with the second discrete read signal; and

setting, during idle time of the memory apparatus, one of the first and the second discrete read signals as a default read signal based at least in part on the respective error corrections.

2. The method of claim 1, wherein error correcting, as part of a test operation during idle time of the memory apparatus, the at least one codeword of the page of user data comprises correcting within an error correction capacity number of errors in the at least one codeword of the page of user data.

3. The method of claim 1, wherein setting one of the first and the second discrete read signals during idle time of the memory apparatus comprises setting one of the first and the second discrete read signals that results in a fewer number of errors according to the error corrections.

4. The method of claim 1, wherein error correcting the at least one codeword of the page of user data includes counting a number of errors corrected.

5. The method of claim 1, wherein the second discrete read signal has a different magnitude than the first discrete read signal.

6. The method of claim 1, wherein error correcting the at least one codeword of the page of user data comprises error correcting all codewords of the page of user data.

7. The method of claim 1, wherein the method includes:

reading a page of user data from the group of memory cells with at least one additional discrete read signal different than the first and the second discrete read signals as part of a test operation during idle time of the memory apparatus; and

error correcting, as part of the test operation during idle time of the memory apparatus, at least one codeword of the page of user data as read with each of the at least one additional discrete read signal;

wherein setting, during idle time of the memory apparatus, one of the first and the second discrete read signals as a default read signal comprises setting one of the first, the second, and the at least one additional discrete read signals as the default read signal.

8. The method of claim 1, wherein the method includes:

reading a page of user data from the group of memory cells with a third discrete read signal different than the first and the second discrete read signals as part of a test operation during idle time of the memory apparatus;

error correcting at least one codeword of the page of data as read with the third discrete read signal as part of a test operation during idle time of the memory apparatus;

reading a page of user data from the group of memory cells with a fourth discrete read signal different than the first, second, and third discrete read signals;

error correcting at least one codeword of the page of data as read with the fourth discrete read signal as part of a test operation during idle time of the memory apparatus; and

setting, during idle time of the memory apparatus, one of the third and the fourth discrete read signals as an additional default read signal based at least in part on the respective error corrections.

9. The method of claim 8, wherein the method includes using the default read signal and the additional default read signal as read signals to distinguish different data states.

10. A memory apparatus, comprising:

a memory including memory cells;

a controller coupled to the memory, wherein the controller is configured to;

read a page of user data from a group of memory cells with a first discrete read signal as part of a test operation during idle time of the memory apparatus;

error correct, as part of the test operation during idle time of the memory apparatus, at least one codeword of the page of user data as read with the first discrete read signal;

read the page of user data from the group of memory cells with a second discrete read signal different than the first discrete read signal as part of the test operation during idle time of the memory apparatus;

error correct, as part of the test operation during idle time of the memory apparatus, at least one codeword of the page of user data as read with the second discrete read signal; and

set, during idle time of the memory apparatus, one of the first and the second discrete read signals as a default read signal based at least in part on the respective error corrections.

11. The memory apparatus of claim 10, wherein the controller is configured to error correct, as part of the test operation during idle time of the memory apparatus, the at least one codeword of the page of user data within an error correction capacity number of errors in the at least one codeword of the page of user data.

12. The memory apparatus of claim 10, wherein the controller is configured to set one of the first and the second discrete read signals during idle time of the memory apparatus that results in a fewer number of errors according to the error corrections.

13. The memory apparatus of claim 10, wherein the controller is configured to count a number of errors corrected as part of error correction of the at least one codeword of the page of user data.

14. The memory apparatus of claim 10, wherein the second discrete read signal has a different magnitude than the first discrete read signal.

15. The memory apparatus of claim 10, wherein the controller is configured to error correct all codewords of the page of user data.

16. The memory apparatus of claim 10, wherein the controller is configured to:

read a page of user data from the group of memory cells with at least one additional discrete read signal different than the first and the second discrete read signals as part of a test operation during idle time of the memory apparatus;

error correct, as part of the test operation during idle time of the memory apparatus, at least one codeword of the page of user data as read with each of the at least one additional discrete read signal; and

set one of the first, the second, and the at least one additional discrete read signals as the default read signal.

17. The memory apparatus of claim 10, wherein the controller is configured to:

read a page of user data from the group of memory cells with a third discrete read signal different than the first and the second discrete read signals as part of a test operation during idle time of the memory apparatus;

error correct at least one codeword of the page of data as read with the third discrete read signal as part of a test operation during idle time of the memory apparatus;

read a page of user data from the group of memory cells with a fourth discrete read signal different than the first, second, and third discrete read signals;

error correct at least one codeword of the page of data as read with the fourth discrete read signal as part of a test operation during idle time of the memory apparatus; and

set, during idle time of the memory apparatus, one of the third and the fourth discrete read signals as an additional default read signal based at least in part on the respective error corrections.

18. The memory apparatus of claim 17, wherein the controller is configured to use the default read signal and the additional default read signal as read signals to distinguish different data states.