TSV substrate structure and the stacked assembly thereof

• US 9,257,338 B2
• Filed: 02/06/2015
• Issued: 02/09/2016
• Est. Priority Date: 11/26/2010
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wang, Chung-Chih, Tzeng, Pei-Jer, Lin, Cha-Hsin, Ku, Tzu-Kun
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US14/615,922
• Publication Number:
  US 20150155204A1
• Time in Patent Office: 368 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81911 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

Claims

1. A method of fabricating a stacked assembly, comprising steps of:

providing a first substrate and a second substrate, each having a cylindrical trench with an extensional part surrounding the cylindrical trench;

forming a barrier layer and a seed layer on the surfaces of the first and second substrates, so that the barrier layer and the seed layer are confirmally formed on sidewalls and bottoms of the cylindrical trenches and the extensional parts;

forming a first conductor layer on the seed layer of the first substrate, so that the first conductor layer under-fills the cylindrical trench and the extensional part of the first substrate, with a recess formed in the first conductor layer in the cylindrical trench;

removing, from top to bottom, a part of the first conductor layer, the barrier layer and the seed layer until a top surface of the first substrate is exposed, so that the recess remains in the first conductor layer in the cylindrical trench;

forming a second conductor layer on the seed layer of the second substrate, so that the second conductor layer over-fills the cylindrical trench and the extensional part of the second substrate, with a protrusion formed on the second conductor layer in the cylindrical trench;

etching to remove a part of the second conductor layer as well as the barrier layer and the seed layer exceeding a top surface of the second substrate, so that the protrusion remains on the second conductor layer in the cylindrical trench;

forming a solder layer on the first and second substrates, so that the solder layer is formed in the recess of the first substrate and on the protrusion of the second substrate; and

stacking the first substrate on the second substrate, with the recess corresponded with the protrusion.

2. The method of claim 1, wherein the removing step is performed by a chemical mechanical planarization process.

3. The method of claim 1, wherein the etching step is performed by a etching process.