Compact semiconductor package and related methods

• US 9,257,396 B2
• Filed: 05/22/2014
• Issued: 02/09/2016
• Est. Priority Date: 05/22/2014
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Uzoh, Cyprian Emeka
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US14/284,969
• Publication Number:
  US 20150340327A1
• Time in Patent Office: 628 Days
• Field of Search: 438/667, 438/691, 257/774, 257/E23.145
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/42 : Wire connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/071 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.

Claims

1. A method of forming a semiconductor package, comprising:

providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;

attaching a first die within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and

forming one or more interconnect lines spaced from the second surface and coupling the first die to at least one of the one or more conductive elements and to at least a conductive via through the first die.

2. The method of claim 1, wherein the forming the one or more interconnect lines includes wire bonding the first die to the at least one of the one or more conductive elements.

3. The method of claim 1, further comprising:

attaching a second die within the first one of the one or more substrate regions at the second surface; and

coupling the second die to the at least one of the one or more conductive elements.

4. The method of claim 1, further comprising:

stacking a second die on the first die within the first one of the one or more substrate regions at the second surface, wherein the second die is electrically coupled to the first die; and

coupling the second die to the at least one of the one or more conductive elements.

5. The method of claim 1, wherein one or more of the one or more conductive elements are electrically isolated and configured to function as a thermal conduction path.

6. A method of forming a semiconductor package, comprising:

providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;

attaching a first die within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and

coupling the first die to at least one of the one or more conductive elements;

wherein providing the substrate including the one or more conductive elements disposed therein comprises;

providing the substrate such that the one or more conductive elements extend from the first surface of the substrate and span part of a distance toward the second surface of the substrate opposite the first surface; and

then

performing an etch process of the second surface of the substrate to expose the one or more conductive elements and thereby form the one or more substrate regions at the second surface.

7. A method of forming a semiconductor package, comprising:

providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;

depositing a first dielectric layer over the second surface of the substrate and the one or more conductive elements;

attaching a first die to the first dielectric layer within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and

coupling the first die to at least one of the one or more conductive elements.

8. The method of claim 7, further comprising:

prior to coupling the first die to at least one of the one or more conductive elements, depositing a second dielectric layer over the second surface of the substrate; and

performing an etch process of the second surface of the substrate to expose an end portion of the at least one of the one or more conductive elements, wherein the exposed end portion of the at least one of the one or more conductive elements is then coupled to the first die.

9. The method of claim 8, further comprising:

prior to coupling the first die to at least one of the one or more conductive elements, removing the second dielectric layer to expose the first die.

10. A method of forming a semiconductor package, comprising:

providing a substrate including one or more conductive elements disposed therein, wherein each conductive element extends from a first surface of the substrate toward a second surface of the substrate opposite the first surface, and wherein each conductive element extends beyond the second surface, the second surface comprising one or more substrate regions not occupied by the one or more conductive elements;

attaching a first die within a first one of the one or more substrate regions at the second surface, such that each conductive element extends beyond at least part of the first die at the second surface; and

coupling the first die to at least one of the one or more conductive elements and to at least a conductive via through the first die;

wherein coupling the first die to the at least one of the one or more conductive elements comprises forming a first redistribution layer (RDL) over the first die, wherein the first RDL couples the first die to the at least one of the one or more conductive elements.

11. The method of claim 10, further comprising:

prior to forming the first RDL, forming a dielectric layer over the first die; and

forming the first RDL over the dielectric layer.

12. The method of claim 11, wherein a first set of electrically conductive paths penetrate the dielectric layer and electrically couple the first RDL to the first die.

13. The method of claim 10, further comprising:

attaching a second die to an exposed outer surface of the first RDL, wherein the second die is electrically coupled to the first RDL, and wherein the second die is electrically coupled to the first die through the first RDL.

14. The method of claim 10, further comprising forming a second RDL over the first surface of the substrate, wherein the second RDL is electrically coupled to the at least one of the one or more conductive elements.

15. A method of forming a compact integrated circuit package, comprising:

forming one or more electrically conductive structures each of which has a first end and a second end, the one or more electrically conductive structures formed within a substrate having a first surface and a second surface opposite the first surface, wherein the second end of each of the one or more electrically conductive structures is exposed and extends beyond the second surface of the substrate to demarcate one or more substrate regions at the second surface not occupied by the one or more electrically conductive structures;

inserting a first die within one of the one or more substrate regions at the second surface not occupied by the one or more electrically conductive structures; and

forming a first redistribution layer (RDL) over the second surface of the substrate and thereby embedding the first die, wherein the first RDL is coupled to the exposed second end of at least one of the one or more electrically conductive structures and to the at least a conductive via through the first die.

16. The method of claim 15, further comprising:

forming a second RDL over the first surface of the substrate, wherein the second RDL is coupled to the first end of each of the one or more electrically conductive structures.

17. The method of claim 15, further comprising:

prior to forming the first RDL, inserting an electronic package within one of the one or more substrate regions at the second surface, wherein the first RDL is electrically coupled to the electronic package.

18. The method of claim 15, further comprising:

prior to forming the first RDL, stacking a second die on the first die within the one of the one or more substrate regions at the second surface, wherein the second die is electrically coupled to the first die, and wherein the first RDL is electrically coupled to the second die.

19. The method of claim 15, further comprising:

prior to forming the first RDL, depositing a dielectric layer over the second surface of the substrate, wherein the dielectric layer covers the first die; and

forming the first RDL over the dielectric layer.

20. The method of claim 19, wherein a first set of electrically conductive paths penetrate the dielectric layer and electrically couple the first RDL to the first die.

21. The method of claim 15, further comprising:

attaching a second die to an exposed outer surface of the first RDL, wherein the second die is electrically coupled to the first RDL, and wherein the second die is electrically coupled to the first die through the first RDL.