Decoupling MIM capacitor designs for interposers and methods of manufacture thereof

• US 9,257,409 B2
• Filed: 04/08/2014
• Issued: 02/09/2016
• Est. Priority Date: 08/12/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tzeng, Kuo-Chyuan, Tu, Kuo-Chi, Wang, Chen-Jong, Lee, Hsiang-Fan
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US14/248,186
• Publication Number:
  US 20140217549A1
• Time in Patent Office: 672 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

Claims

1. A device comprising:

an interposer, the interposer having a decoupling metal-insulator-metal (MIM) capacitor formed therein, wherein the decoupling MIM capacitor comprises a bottom electrode, a capacitor dielectric over the bottom electrode, and a top electrode over the capacitor dielectric, wherein the top electrode has a first portion having a first width and a second portion having a second width, the first width being larger than the second width;

a first contact pad on a first surface of the interposer;

a second contact pad on a second surface of the interposer, the second surface being opposite to the first surface; and

an integrated circuit die mounted on the first contact pad, the decoupling MIM capacitor being electrically coupled between the integrated circuit die and the second contact pad.

2. The device of claim 1, wherein the interposer further comprises:

a substrate, the substrate having a through-substrate vias (TSV) therein;

a first metallization layer over the substrate and a second metallization layer over the first metallization layer, wherein at least a portion of the first metallization layer is in direct contact with the TSV;

a bottom plate pick-up in the first metallization layer, the bottom plate pick-up being directly coupled to the bottom electrode; and

a top plate pick-up in the second metallization layer, the top plate pick-up being coupled to the top electrode.

3. The device of claim 2, wherein the top plate pick-up is coupled to the top electrode using a via.

4. The device of claim 2, wherein the top plate pick-up is laterally coupled to the top electrode.

5. The device of claim 2, wherein the capacitor dielectric has a first plurality of portions parallel to the first metallization layer and a second plurality of portions perpendicular to the first metallization layer.

6. The device of claim 1, wherein the interposer is free from active circuitry.

7. The device of claim 1, wherein the decoupling MIM capacitor is formed in a trench, the bottom electrode extending from a bottom of the trench along a sidewall of the trench, the top electrode extending from further from the bottom of the trench along the sidewall of the trench than the bottom electrode.

8. A device comprising:

an interposer, the interposer comprising;

a substrate, the substrate having one or more through-substrate vias (TSVs) and a contact pad;

a first metallization layer over the substrate and a second metallization layer over the first metallization layer, wherein portions of the first metallization layer is in direct contact with respective ones of the one or more TSVs; and

a decoupling metal-insulator-metal (MIM) capacitor in the second metallization layer, the decoupling MIM capacitor comprising a bottom electrode, a capacitor dielectric over the bottom electrode, and a top electrode over the capacitor dielectric; and

an integrated circuit die mounted to the interposer, wherein the decoupling MIM capacitor is electrically coupled between the integrated circuit die and the contact pad.

9. The device of claim 8, further comprising a redistribution layer (RDL) over the second metallization layer.

10. The device of claim 8, wherein the top electrode comprises a first top electrode material and a second top electrode material over the first top electrode material, the first top electrode material being different from the second top electrode material.

11. The device of claim 8, wherein the substrate is free from active circuitry.

12. The device of claim 8, further comprising a bottom plate pick-up in the first metallization layer, wherein the bottom plate pick-up is directly coupled to portions of the bottom electrode.

13. The device of claim 8, further comprising a top plate pick-up in a third metallization layer, the third metallization layer being over the second metallization layer, wherein the top plate pick-up is coupled to the top electrode.

14. A device comprising:

a substrate, the substrate having one or more contact pads;

one or more metallization layers over the substrate;

a bottom plate pick-up in a first metallization layer of the one or more metallization layers;

a decoupling metal-insulator-metal (MIM) capacitor in the one or more metallization layers, the decoupling MIM capacitor comprising a first electrode, a second electrode, and a capacitor dielectric interposed between the first electrode and the second electrode;

a top plate pick-up in a second metallization layer of the one or more metallization layers, the second metallization layer being over the first metallization layer; and

an integrated circuit die electrically coupled to a first contact pad of the one or more contact pads, wherein the decoupling MIM capacitor is electrically coupled between the integrated circuit die and a second contact pad of the one or more contact pads.

15. The device of claim 14, wherein the top plate pick-up is coupled to the first electrode using a via.

16. The device of claim 14, wherein the top plate pick-up is directly coupled to the first electrode.

17. The device of claim 14, wherein the first electrode comprises a first electrode material and a second electrode material over the first electrode material, the first electrode material being different from the second electrode material.

18. The device of claim 14, wherein the second electrode has a first plurality of portions parallel to the first metallization layer, the first plurality of portions being directly coupled to the bottom plate pick-up.

19. The device of claim 14, wherein a bottommost surface of the top plate pick-up is lower than a topmost surface of the first electrode.

20. The device of claim 14, wherein a bottommost surface of the top plate pick-up is higher than a topmost surface of the first electrode.