Display panel and manufacturing method thereof

• US 9,257,565 B2
• Filed: 07/25/2014
• Issued: 02/09/2016
• Est. Priority Date: 07/25/2013
• Status: Active Grant

• Current Assignee: Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Ye Xin Technology Consulting Co Ltd
• Inventors: Shih, Po-Li
• Primary Examiner(s): Seven, Evren
• Application Number:
  US14/340,573
• Publication Number:
  US 20150031168A1
• Time in Patent Office: 564 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A display panel manufacturing method includes forming a gate electrode on a substrate and a gate insulator, a semiconductor layer, and an etch stop layer covering the gate electrode. A photoresist layer covering on the etch stop layer is pattern from two opposite side of the substrate by two photolithography processes to form a photoresist pattern. The etch stop layer is dry etched to form an etch stop pattern via the photoresist pattern. The photoresist pattern is formed again by two photolithography processes. The semiconductor layer is wet etched to form a semiconductor pattern via the photoresist pattern. A source electrode and a drain electrode is formed corresponding to two opposite sides of the gate electrode to orderly cover the etch pattern, the semiconductor pattern, and the gate insulator.

Claims

1. A method of manufacturing a display panel, the method comprising, in sequence:

providing a substrate, the substrate comprising a first surface and a second surface opposite to the first surface;

forming a gate electrode extending along a first direction on the first surface;

forming a gate insulator, a semiconductor layer, and an etch stop layer to cover the gate electrode;

forming a photoresist layer to cover the etch stop layer;

patterning the photoresist layer by exposing the photoresist layer to light incident to the first surface through a first mask, thereby forming a first photoresist pattern;

patterning the first photoresist pattern by exposing the first photoresist pattern to light incident the second surface, using the gate electrode as a second mask, thereby forming a second photoresist pattern from the second surface by using the gate electrode as a second mask;

etching the etch stop layer by a dry etch process using the second photoresist pattern as a first etching mask to form an etch stop pattern having a smaller surface area than the second photoresist pattern;

removing the second photoresist pattern remaining after the dry etch process and forming a second photoresist layer to cover the etch stop pattern and the semiconductor layer;

patterning the second photoresist layer by exposing the second photoresist layer to light incident first surface using the first mask, thereby forming a fourth photoresist pattern on the etch stop pattern;

patterning the fourth photoresist pattern by exposing the fourth photoresist pattern to light incident the second surface using the gate electrode as the second mask thereby forming a fifth photoresist pattern;

etching the semiconductor layer by a second wet etch process using the fifth photoresist pattern as a second etching mask to form a semiconductor pattern corresponding to the second photoresist pattern;

removing the forth photoresist pattern remaining after the second wet etch process; and

forming a source electrode and a drain electrode respectively at two symmetric sides of the gate electrode, and both of the source electrode and drain electrode covering the etch stop pattern, the semiconductor pattern, and the gate insulator.

2. The manufacturing method of claim 1, wherein the semiconductor layer is made of indium gallium zinc oxide.

3. The manufacturing method of claim 1, wherein a first area covered by the first photoresist pattern is a rectangular area, a longitudinal direction of the first area is extended along a second direction perpendicular to the first direction, and the first area comprises a pair of protruding portions respectively extending out corresponding to two opposite sides of the gate electrode.

4. The manufacturing method of claim 3, wherein a second area covered by the second photoresist pattern is formed by removing the pair of protruding portions comparing with the first area.

5. The manufacturing method of claim 3, wherein the etch stop pattern is shortened about 1.75 micrometer along the second direction by the dry etch process.

6. The manufacturing method of claim 3, wherein an area covered by the etch stop pattern is defined as a channel area of the semiconductor layer.

7. The manufacturing method of claim 6, wherein the second direction is defined as a longitudinal direction of the channel area.

8. The manufacturing method of claim 1, wherein the etch stop layer is made of silicon oxide.

9. The manufacturing method of claim 1, wherein an etching solution of the wet etch process is oxalic acid.

10. The manufacturing method of claim 1, wherein the substrate is a transparent glass substrate.