Memory gate first approach to forming a split gate flash memory cell device

• US 9,257,571 B1
• Filed: 09/05/2014
• Issued: 02/09/2016
• Est. Priority Date: 09/05/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Yuan-Tai, Chang, Yu-Hsing, Wu, Chang-Ming, Liu, Shih-Chang
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US14/477,911
• Time in Patent Office: 522 Days
• Field of Search: 257/314
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A split gate flash memory cell device with a line-shaped charge trapping dielectric structure is provided. A semiconductor substrate includes a first source/drain region and a second source/drain region. A select gate and a memory gate are spaced over the semiconductor substrate between the first and second source/drain regions. A line-shaped charge trapping dielectric structure is arranged between the semiconductor substrate and the memory gate. A method for manufacturing the split gate flash memory cell device is also provided.

Claims

1. A split gate flash memory cell device, comprising:

a semiconductor substrate including a first source/drain region and a second source/drain region;

a select gate and a memory gate spaced over the semiconductor substrate between the first and second source/drain regions;

a line-shaped charge trapping dielectric structure arranged between the semiconductor substrate and the memory gate; and

a sidewall layer laterally spaced from the select and memory gates, and confined to sidewalls of spacer layers laterally spacing the sidewall layer from the select and memory gates;

wherein the line-shaped charge trapping dielectric structure includes;

a tunneling structure;

a memory gate dielectric structure arranged over the tunneling structure; and

a charge storage structure arranged over the tunneling structure between the tunneling structure and the memory gate dielectric structure.

2. The split gate flash memory cell device according to claim 1, further including:

an inter-gate spacer arranged between neighboring sidewalls of the select and memory gates.

3. The split gate flash memory cell device according to claim 1, wherein the line-shaped charge trapping dielectric structure begins approximately even with a first sidewall of the memory gate, extends linearly towards a second sidewall of the memory gate opposite the first sidewall, and ends approximately even with the second sidewall.

4. The split gate flash memory cell device according to claim 1, wherein the tunneling and memory gate dielectric structures includes oxides, and the charge storage structure includes a nitride layer or a plurality of silicon dots.

5. The split gate flash memory cell device according to claim 1, further including:

an inter-layer dielectric (ILD) structure arranged over and surrounding the select and memory gates, and the line-shaped charge trapping dielectric structure; and

conductive contacts extending through the ILD structure to the first and second source/drain regions.

6. The split gate flash memory cell device according to claim 1, further comprising:

a spacer layer arranged on opposing sidewalls of the line-shaped charge trapping dielectric structure and the memory gate, and laterally spacing the select gate from the memory gate; and

a dielectric layer confined directly under the spacer layer and the memory gate;

wherein the line-shaped charge trapping dielectric structure includes a region of the dielectric layer that is directly under the memory gate.

7. The split gate flash memory cell device according to claim 1, wherein the select gate and the memory gate have substantially co-planar upper surfaces.

8. A method for manufacturing a split gate flash memory cell device, the method comprising:

forming a charge trapping dielectric layer and a memory gate layer over a semiconductor substrate;

performing a first etch through the charge trapping dielectric layer to form a memory gate and to form a line-shaped charge trapping dielectric structure between the memory gate and the semiconductor substrate;

forming a conformal select gate layer over the line-shaped charge trapping dielectric structure and the memory gate; and

performing a second etch through the conformal select gate layer to form a select gate over the semiconductor substrate adjacent to the memory gate.

9. The method according to claim 8, further including:

forming the memory gate simultaneously with a second memory gate, the memory gate and the second memory gate spaced over the semiconductor substrate with a central region between the memory gate and the second memory gate;

forming the line-shaped charge trapping dielectric structure simultaneously with a second charge trapping dielectric structure, the second charge trapping dielectric structure being line-shaped and arranged between the second memory gate and the semiconductor substrate; and

forming the select gate simultaneously with a second select gate in the central region on opposite sides of the central region, the select gate adjacent to the memory gate and the second select gate adjacent to the second memory gate.

10. The method according to claim 8, further including:

forming an inter-gate spacer between neighboring sidewalls of the select and memory gates.

11. The method according to claim 8, further including:

forming the line-shaped charge trapping dielectric structure beginning approximately even with a first sidewall of the memory gate, extending linearly towards a second sidewall of the memory gate opposite the first sidewall, and ending approximately even with the second sidewall.

12. The method according to claim 8, further including:

forming a tunneling layer, a charge storage layer, a memory gate dielectric layer, and the memory gate layer over the semiconductor substrate in that order; and

performing a first sub-etch through the tunneling, charge storage, memory gate dielectric, and memory gate layers to form the memory gate.

13. The method according to claim 12, further including:

performing a second sub-etch through the tunneling layer to form the line-shaped charge trapping dielectric structure.

14. The method according to claim 12, further including:

forming the tunneling layer and the memory gate dielectric layers with oxides; and

forming the charge storage layer with a nitride or a plurality of silicon dots.

15. The method according to claim 8, further including:

forming the line-shaped charge trapping dielectric structure and the memory gate with continuous sidewalls.

16. The method according to claim 8, further including:

forming a select gate dielectric structure between the semiconductor substrate and the select gate; and

forming the select gate dielectric structure and the select gate with continuous sidewalls.

17. The method according to claim 8, further including:

forming a first source/drain region in the semiconductor substrate adjacent to the memory gate and a second source/drain region in the semiconductor substrate adjacent to the select gate;

forming an inter-layer dielectric (ILD) structure over and surrounding the select and memory gates, and the line-shaped charge trapping dielectric structure; and

forming conductive contacts extending through the ILD structure to the first and second source/drain regions.

18. A method for manufacturing a split gate flash memory cell device, the method comprising:

forming a memory gate over a semiconductor substrate;

forming a line-shaped charge trapping dielectric structure between the memory gate and the semiconductor substrate, wherein forming the line-shaped charge trapping dielectric structure comprises forming a plurality of layers that are stacked between the memory gate and the semiconductor substrate and that are confined directly under the memory gate;

forming a select gate over the semiconductor substrate adjacent to the memory gate;

forming a sidewall layer laterally spaced from the select and memory gates, and confined to sidewalls of spacer layers laterally spacing the sidewall layer from the select and memory gates; and

performing a planarization into the memory gate and the select gate to co-planarize upper surfaces of the memory gate and the select gate.

19. The method according to claim 18, wherein forming the line-shaped charge trapping dielectric structure comprises:

forming a tunneling structure;

forming a charge storage structure over the tunneling structure; and

forming a memory gate dielectric structure over the charge storage structure.

20. The method according to claim 18, further comprising:

forming a spacer layer on opposing sidewalls of the line-shaped charge trapping dielectric structure and the memory gate, and laterally spacing the select gate from the memory gate; and

forming a dielectric layer confined directly under the spacer layer and the memory gate;

wherein the line-shaped charge trapping dielectric structure includes a region of the dielectric layer that is directly under the memory gate.