Synchronized logic circuit

• US 9,257,985 B2
• Filed: 04/01/2015
• Issued: 02/09/2016
• Est. Priority Date: 04/30/2014
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Halberstadt, Hans
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US14/676,722
• Publication Number:
  US 20150318857A1
• Time in Patent Office: 314 Days
• Field of Search: 327/141, 326/93
• US Class Current: 1/1
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Consistent with an example embodiment, the disclosed includes a synchronized logic circuit comprising: an input module; an output module; a decision logic module connected between the input and output modules and configured to provide a next output state to the output module dependent on a current input state provided from the input and output modules; a clock module connected to the input and output modules and configured to provide a clock signal for synchronizing operation of the input and output modules; and an input detection module connected to the input module and configured to provide an enable signal to the clock module on detection of a change in an input provided to the input module, wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal from the input detection circuit.

Claims

1. A synchronised logic circuit comprising:

an input module;

an output module;

a decision logic module connected between the input and output modules and configured to provide a next output state to the output module dependent on a current input state provided from the input and output modules;

a clock module connected to the input and output modules and configured to provide a clock signal for synchronising operation of the input and output modules; and

an input detection module connected to the input module and configured to provide an enable signal to the clock module on detection of a change in an input provided to the input module,

wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal from the input detection circuit.

2. The synchronised logic circuit of claim 1 wherein the input detection module is configured to compare an output state of the input module with an input state of the input module and provide the enable signal to the clock module when the input and output states of the input module are unequal.

3. The synchronised logic circuit of claim 1, comprising an output detection module connected to the output module and configured to provide an enable signal to the clock module on detection of a change in an output provided by the output module, wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal from the output detection circuit.

4. The synchronised logic circuit of claim 3 wherein the output detection module is configured to compare an output state of the output module with an input state of the output module and provide the enable signal to the clock module when the input and output states of the output module are unequal.

5. The synchronised logic circuit of claim 3, wherein the clock module is configured to provide a clock signal only upon receiving an enable signal from either or both of the input and output detection modules.

6. The synchronised logic circuit of claim 1, wherein the logic circuit is configured to operate as a Moore type state machine.

7. The synchronised logic circuit of claim 1, wherein the logic circuit is configured to operate as a Mealy type state machine, the synchronised logic circuit comprising a further logic module connected to the output module and configured to provide an output state dependent on the output state of the output module and the input state of the input module.

8. The synchronised logic circuit of claim 1, wherein the input and output modules comprise a flip-flop configured to transfer an input state to an output state upon receiving a clock signal.

9. A logic circuit structure comprising first and second synchronised logic circuits according to claim 1, wherein the output module of the first synchronised logic circuit is connected to the input module of the second synchronised logic circuit.

10. A switched mode power supply comprising a synchronised logic circuit or logic circuit structure according to claim 1, wherein the synchronised logic circuit or logic structure is configured to operate a switching state of the power supply.

11. A digital communications device comprising a synchronised logic circuit or logic circuit structure according to claim 1, wherein the synchronised logic circuit or logic structure is configured to operate a digital communications protocol.

12. A method of operating a synchronised logic circuit according to claim 1, comprising the sequential steps of:

the input detection module detecting a change in the input provided to the input module;

the input detection module providing an enable signal to the clock module;

the clock module providing a clock pulse signal to the input and output modules;

the input and output modules each transferring an input state to an output state in response to the clock pulse; and

the decision logic responding to the output state of the input and output modules by providing a next output state to the output module.

13. The method of claim 12 comprising the further sequential steps of:

the output detection module detecting a change in the output provided by the output module;

the output detection module providing an enable signal to the clock module;

the clock module providing a clock pulse to the input and output modules;

the input and output modules each transferring an input state to an output state in response to the clock pulse; and

the decision logic responding to the output state of the input and output modules by providing a next output state to the output module.