Method and apparatus for low power chip-to-chip communications with constrained ISI ratio

• US 9,258,154 B2
• Filed: 08/03/2015
• Issued: 02/09/2016
• Est. Priority Date: 02/02/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Hormati, Ali, Shokrollahi, Amin, Ulrich, Roger
• Primary Examiner(s): ODOM, CURTIS B
• Application Number:
  US14/816,899
• Publication Number:
  US 20150341193A1
• Time in Patent Office: 190 Days
• US Class Current: 1/1
• CPC Class Codes: H04J 13/004 Orthogonal
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4919 using balanced multilevel codes H04L25/4927 takes precedence

Abstract

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

Claims

1. A method comprising:

receiving a set of symbols of a reduced-alphabet codeword, the reduced-alphabet codeword representing a weighted sum of sub-channel code vectors wherein a weighting of each sub-channel code vector is based in part on a corresponding antipodal weight determined by a corresponding input bit in a set of input bits, and wherein the sub-channel code vectors form a reduced-alphabet weight matrix, and are mutually orthogonal to a common mode vector; and

,

forming a set of comparator outputs corresponding to the set of input bits, wherein each comparator output is formed using a respective multi-input comparator (MIC), wherein each respective MIC receives a subset of the symbols and has a set of input weights determined by a respective sub-channel code vector.

2. The method of claim 1, wherein the symbols of the reduced-alphabet codeword have values selected from the normalized set of symbol values {+1, +⅓

, −

⅓

, −

1}.

3. The method of claim 1, wherein the reduced-alphabet codeword comprises 6 symbols.

4. The method of claim 1, wherein the reduced-alphabet weight matrix is represented by a Glasswing coding matrix A:

5. The method of claim 4, wherein rows 2-6 represent the sub-channel code vectors.

6. The method of claim 1, wherein at least one comparator output represents an embedded clock signal.

7. The method of claim 1, wherein for each set of input weights, a sum of positive input weights is equal to 1.

8. The method of claim 1, further comprising generating a set of output bits by slicing the set of comparator outputs according to a reference voltage.

9. The method of claim 8, wherein at least one comparator output is sliced according a to a reference voltage that is greater than or less than 0.

10. The method of claim 8, wherein at least one comparator output is sliced according to a reference voltage equal to 0.

11. An apparatus comprising:

a multi-wire communication bus configured to receive a set of symbols of a reduced-alphabet codeword, the reduced-alphabet codeword representing a weighted sum of sub-channel code vectors wherein a weighting of each sub-channel code vector is based in part on a corresponding antipodal weight determined by a corresponding input bit in a set of input bits, and wherein the sub-channel code vectors form a reduced-alphabet weight matrix, and are mutually orthogonal to a common mode vector; and

,

a plurality of multi-input comparators (MICs) configured to form a set of comparator outputs corresponding to the set of input bits, wherein each comparator output is formed using a respective MIC, wherein each respective MIC receives a subset of the symbols and has a set of input weights determined by a respective sub-channel code vector.

12. The apparatus of claim 11, wherein the symbols of the reduced-alphabet codeword have values selected from the normalized set of symbol values {+1, +⅓

, −

⅓

, −

1}.

13. The apparatus of claim 11, wherein the reduced-alphabet codeword comprises 6 symbols.

14. The apparatus of claim 11, wherein the reduced-alphabet weight matrix is represented by a Glasswing coding matrix A:

15. The apparatus of claim 14, wherein rows 2-6 represent the sub-channel code vectors.

16. The apparatus of claim 11, wherein at least one comparator output represents an embedded clock signal.

17. The apparatus of claim 11, wherein for each set of input weights, a sum of positive input weights is equal to 1.

18. The apparatus of claim 11, further comprising a plurality of slicers configured to generate a set of output bits by slicing the set of comparator outputs according to a reference voltage.

19. The apparatus of claim 18, wherein at least one comparator output is sliced according a to a reference voltage that is greater than or less than 0.

20. The apparatus of claim 18, wherein at least one comparator output is sliced according to a reference voltage equal to 0.