PoP structures including through-assembly via modules

• US 9,258,922 B2
• Filed: 01/18/2012
• Issued: 02/09/2016
• Est. Priority Date: 01/18/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chih-Hua, Chen, Chen-Shien, Hsiao, Ching-Wen
• Primary Examiner(s): Wu, Jerry
• Assistant Examiner(s): Augustin, Christopher L
• Application Number:
  US13/352,937
• Publication Number:
  US 20130182402A1
• Time in Patent Office: 1,483 Days
• Field of Search: 361/760, 361/790, 361/792, 361/795, 361/804, 361/807, 361809-811
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 7/1061 : co-operating by abutting

Abstract

A device includes a Through-Assembly Via (TAV) Module, which includes a substrate, a plurality of through-vias penetrating through the substrate, and a second plurality of metal posts at a bottom surface of the TAV module and electrically coupled to the plurality of through-vias. A polymer includes a first portion between and contacting sidewalls of the first package component and the TAV module, a second portion disposed between the first plurality of metal posts, and a third portion disposed between the second plurality of metal posts. A first plurality of Redistribution Lines (RDLs) is underlying a bottom surface of the second and the third portions of the polymer. A second plurality of RDLs is over the first package component and the TAV module. The first plurality of RDLs is electrically coupled to the second plurality of RDLs through the plurality of through-vias in the TAV module.

Claims

1. A device comprising:

a first package component;

a first plurality of metal posts at a bottom surface of the first package component and electrically coupled to the first package component;

a Through-Assembly Via (TAV) Module comprising;

a substrate;

a strip-shaped via in the substrate, wherein the strip-shaped via is electrically floating;

a plurality of through-vias penetrating through the substrate, wherein each of the plurality of through-vias comprises a straight sidewall extending from a top surface to a bottom surface of the substrate; and

a second plurality of metal posts at a bottom surface of the TAV module and electrically coupled to the plurality of through-vias;

a polymer comprising;

a first portion between and contacting sidewalls of the first package component and the TAV module;

a second portion disposed between the first plurality of metal posts; and

a third portion disposed between the second plurality of metal posts;

a first plurality of Redistribution Lines (RDLs) underlying a bottom surface of the second and the third portions of the polymer; and

a second plurality of RDLs over the first package component and the TAV module, wherein the first plurality of RDLs is electrically coupled to the second plurality of RDLs through the plurality of through-vias in the TAV module.

2. The device of claim 1, wherein the first package component comprises a semiconductor substrate having a top surface level with the top surface of the substrate of the TAV module.

3. The device of claim 2 further comprising a dielectric layer over and contacting the top surface of the semiconductor substrate of the first package component, the top surface of the substrate of the TAV module, and the first portion of the polymer.

4. The device of claim 1, wherein the TAV module is free from active devices therein.

5. The device of claim 1, wherein the substrate of the TAV module is a dielectric substrate.

6. The device of claim 1, wherein the plurality of through-vias further comprises:

a first plurality of through-vias interconnected to form a first capacitor plate of a capacitor; and

a second plurality of through-vias interconnected to form a second capacitor plate of the capacitor.

7. A device comprising:

a bottom package comprising;

a package substrate;

a plurality of connectors over the package substrate;

a package comprising;

a device die;

a Through-Assembly Via (TAV) module substantially level with the device die, wherein the TAV module is free from active devices therein, and wherein the TAV module comprises a substrate and a plurality of through-vias penetrating through the substrate, wherein the plurality of through-vias comprises strip-shaped vias, with alternating ones of the strip-shaped vias interconnected to form capacitor plates of a capacitor; and

a molding compound contacting a bottom surface of the device die, a bottom surface of the TAV module, and sidewalls of the device die and the TAV module; and

a first plurality of Redistribution Lines (RDLs) under the molding compound and electrically coupled to the device die and the plurality of through-vias in the TAV module, wherein the first plurality of RDLs is bonded to the package substrate through the plurality of connectors; and

a top package component bonded to the bottom package.

8. The device of claim 7, wherein the package in the bottom package further comprises:

a dielectric layer contacting a top surface of the device die and a top surface of the TAV module; and

a second plurality of RDLs over the dielectric layer and coupled to the plurality of through-vias in the TAV module, wherein the second plurality of RDLs is bonded to the top package component.

9. The device of claim 8, wherein the top surface of the device die is level with the top surface of the TAV module.

10. The device of claim 7, wherein each of the plurality of through-vias comprises a straight sidewall extending from a top surface to a bottom surface of the substrate.

11. The device of claim 7 further comprising an additional TAV module level with the TAV module, wherein the additional TAV module is spaced apart from the TAV module by a portion of the molding compound.

12. The device of claim 7, wherein the substrate of the TAV module is a dielectric substrate.

13. The device of claim 7, wherein one of the plurality of through-vias is electrically floating.

14. A device comprising:

a package comprising;

a device die;

a Through-Assembly Via (TAV) module free from active devices and passive devices therein, wherein the TAV module comprises a first substrate and a plurality of through-vias penetrating through the first substrate, wherein the plurality of through-vias further comprises;

a first plurality of through-vias interconnected to form a first capacitor plate of a capacitor; and

a second plurality of through-vias interconnected to form a second capacitor plate of the capacitor; and

a molding compound encircling each of the device die and the TAV module; and

a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs electrically coupled to the plurality of through-vias, wherein the first plurality of RDLs and the second plurality of RDLs are on opposite sides of the plurality of through-vias.

15. The device of claim 14, wherein the molding compound comprises a first surface coplanar with a second surface of the first substrate and a third surface of a second substrate of the device die.

16. The device of claim 15, wherein the molding compound comprises a fourth surface opposite to the first surface, wherein the fourth surface is coplanar with surfaces of the plurality of through-vias, and the device die comprises a plurality of metal posts comprising surfaces coplanar with the fourth surface of the molding compound.

17. The device of claim 15, wherein each of the first substrate and the second substrate is a semiconductor substrate.

18. The device of claim 15 further comprising a polymer layer contacting the first surface of the molding compound, wherein the plurality of through-vias penetrates through the polymer layer.