Remote memory access functionality in a cluster of data processing nodes

• US 9,262,225 B2
• Filed: 12/27/2012
• Issued: 02/16/2016
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Calxeda Inc.
• Original Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Inventors: Davis, Mark Bradley, Evans, Barry Ross, Borland, David James
• Primary Examiner(s): Rinehart, Mark
• Assistant Examiner(s): Hunt, Kenneth P
• Application Number:
  US13/728,308
• Publication Number:
  US 20140359044A1
• Time in Patent Office: 1,146 Days
• Field of Search: 709/213, 709214-219, 710/22, 710/26, 714147-153
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 45/74 Address processing for routing
• CPC Class Codes: H04L 45/74591 using content-addressable memories [CAM]
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/253 using establishment or release of connections between ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/351 : for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/356 : for storage area networks
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02B 70/30 : Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 : Reducing energy consumption in communication networks

Abstract

A server apparatus comprises a plurality of server on a chip nodes interconnected to each other through a node interconnect fabric. Each one of the server on a chip nodes has respective memory resources integral therewith. Each one of the server on a chip nodes has information computing resources accessible by one or more data processing systems. Each one of the server on a chip nodes is configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the server on a chip nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the server on a chip nodes thereto based on a workload thereof.

Claims

1. A server card system, comprising:

a first server on a chip node card having a node density configured to enable the first server on a chip node card to provide information computing resources to one or more data processing systems; and

a second server on a chip node card having a memory configuration configured to enable memory resources of the second server on a chip node card to be allocated to one or more nodes of the first server on a chip node card, wherein the second server on a chip node card is configured to;

cause a first portion of the memory resources to be allocated to a first one of the nodes of the first server on a chip node card as a private memory resource; and

cause a second portion of the memory resources to be allocated to a plurality of the nodes of the first server on a chip node card as a shared memory resource.

2. The server card system of claim 1, wherein the second server on a chip node card is further configured to:

assess a workload of a particular one of the nodes of the first server on a chip node card; and

allocate an amount of the memory resources of the second server on a chip node card based on the workload.

3. The server card system of claim 1, wherein:

the second server on a chip node card comprises a plurality of server on a chip nodes;

the memory resources of the second server on a chip node card are accessible by each one of the plurality of server on a chip nodes of the second server on a chip node card; and

each one of the plurality of nodes of the second server on a chip node card can access a portion of the memory resources of the second server on a chip node card and selectively allocate the respective portion of the memory resources to one or more of the nodes of the first server on a chip node card.

4. The server card system of claim 1, wherein:

the nodes of the first server on a chip node card are each configured for inter-node communication via a node interconnect fabric established therebetween; and

the memory resources of the second server on a chip node card are allocated to the nodes of the first server on a chip node card via the node interconnect fabric.

5. The server card system of claim 4, wherein the second server on a chip node card is further configured to:

assess a workload of a particular one of the nodes of the first server on a chip node card; and

allocate an amount of the memory resources of the second server on a chip node card based on the workload.

6. A server apparatus, comprising:

a plurality of server on a chip nodes interconnected to each other through a node interconnect fabric;

wherein each one of the server on a chip nodes has respective memory resources integral therewith;

wherein each one of the server on a chip nodes has information computing resources accessible by one or more data processing systems;

wherein each one of the server on a chip nodes is configured with memory access functionality that enables allocation of at least a portion of the memory resources thereof to one or more other ones of the server on a chip nodes based on a workload of the one or more other ones of the server on a chip nodes;

wherein a first portion of the memory resources is allocated to a first one of the plurality of server on a chip nodes as a private memory resource; and

wherein a second portion of the memory resources is allocated to a plurality of the plurality of server on a chip nodes as a shared memory resource.

7. The server apparatus of claim 6, wherein at least one of the server on a chip nodes is further configured to:

assess the workload of the one or more other ones of the server on a chip nodes.

8. The server apparatus of claim 6, wherein the respective memory resources of each one of the server on a chip nodes is part of a pool of memory resources accessible by each one of the server on a chip nodes.

9. The server apparatus of claim 6, wherein:

a first portion of the respective memory resources of a particular one of the server on a chip nodes is the private memory resource; and

a second portion of the respective memory resources of the particular one of the server on a chip nodes is the shared memory resource.

10. The server apparatus of claim 9, wherein at least one of the server on a chip nodes is further configured to:

assess the workload of the particular one of the server on a chip nodes of the server apparatus; and

allocate an amount of the memory resources of another one of the server on a chip nodes of the server apparatus to the particular one of the server on a chip nodes as the private memory resource thereof based on the workload of the particular one of the server on a chip nodes of the server apparatus.

11. A data processing facility, comprising:

a server rack having a mounting structure configured to individually receive a plurality of server rack chassis;

a first server rack chassis engaged with the mounting structure of the server rack, wherein the first server rack chassis includes a first plurality of server on a chip nodes having a node density configured to enable the server on a chip nodes of the first server rack chassis to provide information computing resources to one or more data processing systems; and

a second server rack chassis engaged with the mounting structure of the server rack, wherein the second server rack chassis includes a second plurality of server on a chip nodes interconnected to the first plurality of server on a chip nodes through a node interconnect fabric, and wherein each one of the second plurality of server on a chip nodes has a memory configuration configured to enable memory resources thereof to be allocated to one or more of the first plurality of server on a chip nodes;

wherein a first portion of the memory resources is configured to be allocated to a first one of the first plurality of server on a chip nodes of the first server rack chassis as a private memory resource; and

wherein a second portion of the memory resources is configured to be allocated to a plurality of the first plurality of server on a chip nodes of the first server rack chassis as a shared memory resource.

12. The data processing facility of claim 11, wherein at least one of the second plurality of server on a chip nodes is further configured to:

assess a workload of a particular one of the first plurality of server on a chip nodes of the first server rack chassis; and

allocate an amount of the memory resources of the second server rack chassis based on the workload.

13. The data processing facility of claim 11, wherein:

the memory resources of the second server rack chassis are accessible by each one of the second plurality of server on a chip nodes; and

each one of the second plurality of server on a chip nodes of the second server rack chassis are configured to access a portion of the memory resources and selectively allocate the portion of the memory resources to one or more of the first plurality of server on a chip nodes of the first server rack chassis.

14. The data processing facility of claim 11, wherein the memory resources are allocated via the node interconnect fabric.

15. The data processing facility of claim 14, wherein at least one of the second plurality of server on a chip nodes is further configured to:

assess a workload of a particular one of the first plurality of server on a chip nodes of the first server rack chassis; and

allocate an amount of the memory resources of the second server rack chassis based on the workload.

16. A server apparatus, comprising:

a central processing unit (CPU) subsystem including a first plurality of server on a chip nodes having a node density configured to enable the CPU subsystem to provide information computing resources to one or more data processing systems, wherein the server on a chip nodes are physically contained in a first physical enclosure unit; and

a memory subsystem operably coupled to the CPU subsystem such that the first plurality of server on a chip nodes are configured to access memory units of the memory subsystem, wherein the memory units are physically contained in a second physical enclosure unit that is external to the first physical enclosure unit;

wherein a first portion of the memory resources is configured to be allocated to a particular one of the first plurality of server on a chip nodes of the CPU subsystem as a private memory resource; and

wherein a second portion of the memory resources is configured to be allocated to a plurality of the first plurality of server on a chip nodes of the CPU subsystem as a shared memory resource.

17. The server apparatus of claim 16, wherein:

the memory subsystem comprises a second plurality of server on a chip nodes;

the memory units of the memory subsystem are accessible by each one of the second plurality of server on a chip nodes; and

the second plurality of server on a chip nodes of the memory subsystem are coupled to the first plurality of server on a chip nodes of the CPU subsystem via a node interconnect fabric.

18. The server apparatus of claim 17 wherein:

each one of the memory units is coupled to one of the second plurality of server on a chip nodes of the memory subsystem by a respective communication link such that each of the second plurality of server on a chip nodes is configured to utilize memory resources of the memory subsystem; and

the communication link of each one of the memory units supports communication of information with a respective one of the second plurality of server on a chip nodes.

19. The server apparatus of claim 17, wherein each one of the second plurality of server on a chip nodes of the memory subsystem is configured to allocate memory resources of one or more of the memory units to one or more of the first plurality of server on a chip nodes of the CPU subsystem.

20. The server apparatus of claim 19, wherein allocation of the memory resources to a particular one of the first plurality of server on a chip nodes is based on a workload of the particular one of the first plurality of server on a chip nodes of the CPU subsystem.

21. The server apparatus of claim 16, wherein the memory units comprise a pool of memory resources accessible by each of a second plurality of server on a chip nodes of the memory subsystem.

22. The server apparatus of claim 16, wherein the memory subsystem comprises a second plurality of server on a chip nodes, and wherein:

a first portion of memory resources of a particular one of the second plurality of server on a chip nodes is the private memory resource; and

a second portion of the memory resources of the particular one of the second plurality of server on a chip nodes is the shared memory resource.

23. The server apparatus of claim 22, wherein allocation of at least a portion of the memory resources of the particular one of the second plurality of server on a chip nodes is based on a workload of another one of the second plurality of server on a chip nodes.