Messaging interruptible blocking wait with serialization

• US 9,262,235 B2
• Filed: 04/07/2011
• Issued: 02/16/2016
• Est. Priority Date: 04/07/2011
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Tillier, Fabian Samuel
• Primary Examiner(s): Onat, Umut
• Application Number:
  US13/082,205
• Publication Number:
  US 20120260262A1
• Time in Patent Office: 1,776 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 12/6418 Hybrid transport

Abstract

Enhanced message passing architectures and libraries include an interruptible wait feature. After a thread X calls a completion-awaiting routine of a message passing interface library, a progress engine executes while the routine is in the blocked condition. A thread Y interrupts the routine before all messaging operations are completed. The interrupted routine returns control to thread X with an indication that the routine'"'"'s completion condition is unsatisfied. The completion-awaiting routine may have the same function signature as a standard MPI routine. In some cases, thread Y interrupts the routine while requesting a lock held by thread X. In some applications, thread X is a communication thread and thread Y is one of multiple worker threads. The interruptible wait feature may be joined by an asynchronous callback feature, which associates a callback with a deterministic execution context.

Claims

1. A process comprising the steps of:

a thread X in an application calling an interruptible completion-awaiting routine of a message passing interface (MPI) library, the called interruptible completion-awaiting routine being configured to return successfully from a blocked condition after a specified message passing completion condition is satisfied, the completion condition specifying a list of requests which have not yet been completed;

a message passing interface library progress engine executing while the interruptible completion-awaiting routine is in the blocked condition;

a thread Y interrupting the interruptible completion-awaiting routine prior to satisfaction of the completion condition; and

the interruptible completion-awaiting routine returning control in response to interruption by the thread Y, as part of an interruptible wait enhancement which (a) is not an asynchronous callback enhancement, (b) allows an interruption of the completion-awaiting routine without canceling the completion-awaiting routine, and wherein the interruptible completion-awaiting routine returns with a completion indicator which indicates that at least one of the listed requests was completed prior to the interruption and also indicates that at least one of the listed requests was not completed prior to the interruption, and (c) allows the application to make progress;

wherein the interruptible wait enhancement of the interrupted completion-awaiting routine returns control to the thread X in conjunction with an indication specifying that more than 1 and less than N messaging operations in the list of N messaging operations had completed when the thread Y interrupted the completion-awaiting routine, with N being an integer greater than 2.

2. The process of claim 1, wherein the interruptible wait enhancement of the interrupted completion-awaiting routine returns control to the thread X in conjunction with an indication of which of the listed requests completed prior to the interruption.

3. The process of claim 1, in which the interruptible completion-awaiting routine is a wait-some routine which has a list of non-blocking requests and wherein the interruptible wait enhancement returns control from the blocked condition after a completion of processing occurs on at least one of the listed requests.

4. The process of claim 1, wherein the thread Y interrupts the interruptible completion-awaiting routine in conjunction with requesting a lock held by the thread X.

5. The process of claim 1, further comprising utilizing a lock for serializing thread calls to the message passing interface library.

6. The process of claim 1, performed in an MPI architecture in which one of the thread X and the thread Y is a communication thread and the other of the thread X and the thread Y is one of multiple worker threads.

7. The process of claim 1, performed in an MPI architecture which complies with at least one of the following standards:

MPI_THREAD_FUNNELED, MPI_THREAD_SERIALIZED.

8. A computer-readable storage memory configured with data and with instructions that when executed cause processor(s) to perform a process for interruptible blocking wait in a messaging architecture, the process comprising the steps of:

a thread X in an application calling an interruptible completion-awaiting routine of a message passing interface library, the called interruptible completion-awaiting routine being configured to return successfully from a blocked condition after a specified message passing completion condition is satisfied, the completion condition specifying a list of N messaging operations which have not yet been completed;

a message passing interface library progress engine executing while the interruptible completion-awaiting routine is in the blocked condition;

a thread Y interrupting the interruptible completion-awaiting routine prior to satisfaction of the completion condition; and

the interrupted completion-awaiting routine returning control to the thread X in conjunction with an indication that the completion condition is unsatisfied;

wherein the interruptible completion-awaiting routine returns control to the thread X in response to interruption by the thread Y as part of an interruptible wait enhancement which (a) is not an asynchronous callback enhancement, (b) allows an interruption of the completion-awaiting routine without canceling the completion-awaiting routine, and wherein the interruptible completion-awaiting routine returns with a completion indicator which indicates that at least one of the listed operations was completed prior to the interruption and also indicates that at least one of the listed operations was not completed prior to the interruption, and (c) allows the application to make progress;

wherein the interruptible wait enhancement of the interrupted completion-awaiting routine returns control to the thread X in conjunction with an indication specifying that more than 1 and less than N messaging operations in the list of N messaging operations had completed when the thread Y interrupted the completion-awaiting routine, with N being an integer greater than 2.

9. The computer-readable storage memory of claim 8, wherein the thread Y interrupts the interruptible completion-awaiting routine in conjunction with requesting a lock held by the thread X.

10. The computer-readable storage memory of claim 8, wherein the process further comprises utilizing a FIFO lock for serializing thread calls to the message passing interface library.

11. The computer-readable storage memory of claim 8, wherein the interruptible completion-awaiting routine has the same function signature as a standard MPI waitsome routine.

12. The computer-readable storage memory of claim 8, wherein the message passing interface library progress engine executes in an MPI architecture which complies with at least one of the following standards:

MPI_THREAD_FUNNELED, MPI_THREAD_SERIALIZED.

13. The computer-readable storage memory of claim 8, wherein the process further comprises utilizing a lock for serializing thread calls to the message passing interface library.

14. A computer system comprising:

at least one logical processor, each logical processor in operable communication with a memory;

an application having at least two threads residing in the memory;

a message passing interface library progress engine residing in the memory;

an unsatisfied completion condition specifying a list of N requests which have not yet been completed; and

an interruptible completion-awaiting routine of a message passing interface library, the interruptible completion-awaiting routine configured to return successfully from a blocked condition in the absence of interruption and when the completion condition is satisfied, the completion-awaiting routine also configured to return control in response to an interruption as part of an interruptible wait enhancement which (a) is not an asynchronous callback enhancement, (b) allows an interruption of the completion-awaiting routine without canceling the completion-awaiting routine, and wherein the interruptible completion-awaiting routine returns with a completion indicator which indicates that at least one of the listed requests was completed prior to the interruption and also indicates that at least one of the listed requests was not completed prior to the interruption, and (c) allows the application to make progress;

wherein the interruptible wait enhancement of the interrupted completion-awaiting routine returns control to a thread X in conjunction with an indication specifying that more than 1 and less than N messaging operations in the list of N messaging operations had completed when a thread Y interrupted the completion-awaiting routine, with N being an integer greater than 2.

15. The system of claim 14, wherein one of the threads is a communication thread of an application having at least two processes, the other thread is a worker thread of the application, and each process comprises a communication thread and multiple worker threads.

16. The system of claim 14, further comprising a lock for use in serializing thread calls to the message passing interface library.

17. The system of claim 14, wherein the system comprises an MPI architecture which complies with at least one of the following standards:

MPI_THREAD_FUNNELED, MPI_THREAD_SERIALIZED.

18. The system of claim 14, wherein the completion-awaiting routine has the same function signature as a standard MPI routine.

19. The system of claim 14, further comprising a message passing interface library request residing in the memory and having a requesting thread identifier which identifies one of the threads.

20. The system of claim 14, wherein the system comprises an MPI architecture which complies with at least an MPI_THREAD_FUNNELED standard.