Inter-processor communication link with manageability port

• US 9,262,375 B1
• Filed: 11/27/2013
• Issued: 02/16/2016
• Est. Priority Date: 03/29/2004
• Status: Expired due to Fees

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Mueller, Peter D.
• Primary Examiner(s): Bengzon, Greg C
• Application Number:
  US14/091,958
• Time in Patent Office: 811 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0742 in a data processing system embedded in a mobile device, e.g. mobile phones, handheld devices
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided.

Claims

1. A system for a wireless device, comprising:

a plurality of microprocessor hardware subsystems, each supporting the wireless device'"'"'s platform for wireless applications;

a manageability control hardware module applying a protocol for communicating over a microprocessor bus of a microprocessor subsystem of the plurality of microprocessor subsystems and perform a management function on the microprocessor subsystem, even when a processor core of the microprocessor subsystem is not responsive to any signal;

inter-processor communication circuitry providing at least a bi-directional communication path to and from at least one peripheral bus of the microprocessor subsystem;

a plurality of multi-channel circuitry of the inter-processor communication circuitry, the plurality of multi-channel circuitry communicating with the at least one peripheral bus of the microprocessor hardware subsystem;

predetermined channel circuitry of an inbound link of the inter-processor communication circuitry, the predetermined channel circuitry receiving a communication used to perform the management function;

command register circuitry storing command data delivered through the inter-processor communication circuitry; and

response register circuitry storing response data from the microprocessor bus, wherein the manageability control hardware module is connected with the command register circuitry and the response register circuitry, the manageability control hardware module determining when the command data is received at the command register circuitry, transmitting a corresponding command signal over the microprocessor bus, receiving a response signal from the microprocessor bus, storing a corresponding response data at the response register circuitry, and transmitting the corresponding response data through the inter-processor communication circuitry.

2. The system according to claim 1, wherein the plurality of multi-channel circuitry include at least a first multi-channel circuitry receiving communications from the at least one peripheral bus of the microprocessor hardware subsystem.

3. The system according to claim 2, wherein the plurality of multi-channel circuitry include at least second multi-channel circuitry of the inter-processor communication circuitry transmitting communications to the at least one peripheral bus of the microprocessor hardware subsystem.

4. The system according to claim 1, wherein the inter-processor communication circuitry includes a data link protocol controlling data flow over the plurality of multi-channel circuitry.

5. The system according to claim 1, wherein the corresponding command signal performs the management function for the microprocessor hardware subsystem.

6. The system according to claim 1, wherein the management function includes at least debugging.

7. The system according to claim 1, wherein the management function includes at least accessing a memory.

8. The system according to claim 1, wherein the management function includes at least accessing configuration registers.

9. The system according to claim 1, wherein the management function includes at least accessing a peripheral device of the microprocessor hardware subsystem.

10. A method for linking communications between processors for a wireless device, comprising:

applying a protocol for communicating over a microprocessor bus of a microprocessor subsystem of a plurality of microprocessor subsystems;

performing by a manageability control module a management function on the microprocessor subsystem, even when a processor core of the microprocessor subsystem is not responsive to any signal;

bi-directionally communicating to and from at least one peripheral bus of the microprocessor subsystem;

communicating, by a plurality of multi-channel links of a inter-processor communication link, with the at least one peripheral bus of the microprocessor subsystem;

receiving a communication used to perform the management function by a predetermined channel of an inbound link of the inter-processor communication link;

storing command data delivered through the inter-processor communication link in a command register;

storing response data from the microprocessor bus in a response register;

determining by a manageability control device when the command data is received at the command register;

transmitting a command signal associated with the command data over the microprocessor bus;

receiving a response signal from the microprocessor bus;

storing a response data associated the response signal at the response register; and

transmitting the corresponding response data through the inter-processor communication link.

11. The method according to claim 10, further comprising:

receiving communications by a first multi-channel link of the inter-processor communication link from the at least one peripheral bus of the microprocessor subsystem.

12. The method according to claim 10, further comprising:

transmitting communications by a second multi-channel link of the inter-processor communication link to the at least one peripheral bus of the microprocessor subsystem.

13. The method according to claim 10, further comprising:

controlling data flow over the plurality of multi-channel links of the inter-processor communication link.

14. The method according to claim 10, further comprising:

performing by the command signal the management function for the microprocessor subsystem.

15. The method according to claim 10, wherein the management function includes at least one of debugging.

16. The method according to claim 10, wherein the management function includes at least one of accessing a memory, accessing configuration registers, and accessing a peripheral device of the microprocessor subsystem.