Integration of lithography apparatus and mask optimization process with multiple patterning process

• US 9,262,579 B2
• Filed: 08/26/2014
• Issued: 02/16/2016
• Est. Priority Date: 04/04/2011
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Chen, Luoqi, Ye, Jun, Chen, Hong
• Primary Examiner(s): Thompson, Annette M
• Application Number:
  US14/468,635
• Publication Number:
  US 20140365983A1
• Time in Patent Office: 539 Days
• Field of Search: 716/53
• US Class Current: 1/1
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70508 Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
• CPC Class Codes: G03F 7/707 Chucks, e.g. chucking or un-chucking operations or structural details
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow.

Claims

1. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns, the method comprising:

identifying a plurality of possible split choices for splitting the pattern into the plurality of sub-patterns;

selecting one of the identified possible split choices based on a prediction of an image of at least one sub-pattern split under each of the split choices, where the image is formed by the at least one sub-pattern after an optical setting of a lithography apparatus used in the lithographic process and the at least one sub-pattern are co-optimized, and where the image is formed by the at least one sub-pattern in a respective split choice and without regard to other sub-patterns in the same respective split choice; and

splitting the pattern into the plurality of sub-patterns under the selected one of the possible split choices.

2. The method of claim 1, wherein selecting includes generating diffraction-maps of split layouts based on the possible split choices.

3. The method of claim 1, wherein selecting includes using diffraction-signature groups in the plurality of sub-patterns as a cost function to determine how the possible split choices affect the co-optimization.

4. The method of claim 1, further comprising optimizing the optical setting of the lithography apparatus using the at least one of the sub-patterns.

5. The method of claim 4, further comprising performing full-chip mask optimization using the optimized optical setting.

6. The method of claim 1, further comprising generating rules for the plurality of possible split choices based on a choice for the optical setting of the lithography apparatus.

7. The method of claim 6, wherein the rules include one or more of minimal pitch size, minimal corner to corner size, minimal line to end size and forbidden pitch size.

8. The method of claim 6, wherein the rules are used to fracture critical parts of the pattern.

9. The method of claim 8, wherein selecting includes creating a graph listing critical groups.

10. The method of claim 9, wherein creating the graph is based on diffraction signature analysis.

11. The method of claim 1, wherein the splitting step comprises rule-based splitting, algorithm based splitting, or a combination of rule-based and algorithm-based splitting.

12. The method of claim 1, wherein a process window of the at least one sub-pattern and a process window of the pattern match.

13. The method of claim 1, wherein the optical setting of the lithography apparatus includes one or more of:

setting and characteristics of an illumination source;

setting and characteristics of a projection optics system; and

, combined setting and characteristics of an illumination source and a projection optics system.

14. The method of claim 1, further comprising using a pattern selection method to select a representative smaller set of portions of design layout containing the pattern from a relatively larger set, wherein the representative smaller set adequately covers characteristic pattern features of the relatively larger set.

15. The method of claim 1, further comprising using a known optical setting to generate rules for splitting the pattern, such that each of the plurality of sub-patterns contain features that are configured to be within a resolution limit of the lithography apparatus.

16. The method of claim 1, further comprising performing optical proximity correction (OPC) to further optimize the sub-patterns after optical settings are fixed as a result of the co-optimization.

17. The method of claim 16, wherein the OPC is performed for full-chip optimization.

18. The method of claim 1, wherein hot spots and warm spots are identified during a verification process that follows at least one iterative cycle of co-optimization.

19. The method of claim 18, wherein the identified hot spots and warm spots are fed back into the splitting step.

20. The method of claim 18, wherein the identified hot spots and warm spots are fed back into a pattern-selection algorithm that selects a representative smaller set of portions of design layout containing the pattern from a relatively larger set, wherein the representative smaller set adequately covers characteristic pattern features of the relatively larger set.

21. The method of claim 1, further comprising sequentially imaging the sub-patterns of the selected one of the split choices on the substrate.