Method and apparatus for integrated circuit design
First Claim
1. A method for integrated circuit (IC) design, comprising steps of:
- receiving an IC design layout having a main feature with an original margin;
generating a first modified margin of said main feature;
performing a first photolithography simulation procedure of said main feature with said first modified margin by using a processor to generate a first contour having a plurality of curves;
obtaining an equation of each of said curves, each of said equations is expressed as a Taylor series;
manipulating each of said equations of said curves by using said processor to obtain a vertex of each of said curves of said first contour;
assigning a first group of target points to said original margin of said main feature, wherein said first group of target points comprising a plurality of target points, each target point of said first group of target points respectively corresponds to one of said vertices;
performing an optical proximity correction (OPC) procedure by using said first group of target points to generate a second modified margin;
wherein said step of generating said first modified margin of said main feature comprises;
dissecting said original margin of said main feature into a plurality of segments, wherein said curves respectively correspond to one of said segments;
assigning a second group of target points to said original margin of said main feature, the second group of target points comprising a plurality of target points; and
performing an another OPC procedure by using said second group of target points to generate said first modified margin;
wherein image errors are compensated for fabricated IC structures by modifying IC design layout structures for enabling photomask fabrication so that a higher fidelity IC main feature is obtained, wherein a second contour is closer to the first group of target points than the first contour, and the second modified margin is structurally different from the first modified margin.
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Abstract
A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.
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Citations
13 Claims
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1. A method for integrated circuit (IC) design, comprising steps of:
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receiving an IC design layout having a main feature with an original margin; generating a first modified margin of said main feature; performing a first photolithography simulation procedure of said main feature with said first modified margin by using a processor to generate a first contour having a plurality of curves; obtaining an equation of each of said curves, each of said equations is expressed as a Taylor series; manipulating each of said equations of said curves by using said processor to obtain a vertex of each of said curves of said first contour; assigning a first group of target points to said original margin of said main feature, wherein said first group of target points comprising a plurality of target points, each target point of said first group of target points respectively corresponds to one of said vertices; performing an optical proximity correction (OPC) procedure by using said first group of target points to generate a second modified margin; wherein said step of generating said first modified margin of said main feature comprises; dissecting said original margin of said main feature into a plurality of segments, wherein said curves respectively correspond to one of said segments; assigning a second group of target points to said original margin of said main feature, the second group of target points comprising a plurality of target points; and performing an another OPC procedure by using said second group of target points to generate said first modified margin; wherein image errors are compensated for fabricated IC structures by modifying IC design layout structures for enabling photomask fabrication so that a higher fidelity IC main feature is obtained, wherein a second contour is closer to the first group of target points than the first contour, and the second modified margin is structurally different from the first modified margin. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9)
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2. An apparatus for integrated circuit (IC) design, comprising:
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a processor; a receiving module, communicatively coupled to said processor and configured to receive an IC design layout having a main feature with an original margin; and a non-transitory computer-readable storage, communicatively coupled to said processor and comprising instructions executable by said processor, said instructions comprising; instructions to generate a first modified margin of said main feature; instructions to perform a first photolithography simulation procedure of said main feature with said first modified margin to generate a first contour having a plurality of curves; instructions to obtain an equation of each of said curves, wherein each said equation is expressed as a Taylor series; instructions to manipulate each said equation of said curves to obtain a vertex of each of said curves; instructions to assign a first group of target points to said original margin of said main feature, wherein each of said first group of target points respectively corresponds to one of said vertices; and instructions to perform an optical proximity correction (OPC) procedure by using said group of target points to generate a second modified margin; wherein said instructions of generating said first modified margin of said main feature comprises; instructions to dissect said original margin of said main feature into a plurality of segments; instructions to assign a second group of target points to said original margin of said main feature; and instructions to perform an another OPC procedure by using said second group of target points to generate said first modified margin; wherein image errors are compensated for fabricated IC structures by modifying IC design layout structures for enabling photomask fabrication so that a higher fidelity IC main feature is obtained, wherein a second contour is closer to the first group of target points than the first contour, and the second modified margin is structurally different from the first modified margin. - View Dependent Claims (10, 11, 12, 13)
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Specification