Data retention flags in solid-state drives

• US 9,263,136 B1
• Filed: 11/26/2013
• Issued: 02/16/2016
• Est. Priority Date: 09/04/2013
• Status: Expired due to Fees

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Zhao, Dengtao, Sun, Yongke, Li, Haibo, Yang, Jui-Yao, Stoev, Kroum
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Radke, Jay
• Application Number:
  US14/090,426
• Time in Patent Office: 812 Days
• Field of Search: 365/185.09, 365/185.18, 365/200, 365/201, 365/210.12
• US Class Current: 1/1
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.

Claims

1. A data storage device comprising:

a non-volatile memory array comprising a plurality of non-volatile memory devices; and

a controller configured to;

write data to a memory unit of the non-volatile memory array;

write a value to a memory indicating a number of bits of the written data programmed in a first of a plurality of logical states;

read the written data from the non-volatile memory array;

determine a number of bits having the first of the plurality of logical states in the read data;

determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data; and

schedule a data refreshing operation for the non-volatile memory array based at least in part on the difference.

2. The data storage device of claim 1, wherein the first of the plurality of logical states corresponds to a value of ‘

0’ and

a second of the plurality of logical states corresponds to a value of ‘

1’

.

3. The data storage device of claim 1, wherein the first of the plurality of logical states corresponds to a value of ‘

1’ and

a second of the plurality of logical states corresponds to a value of ‘

0’

.

4. The data storage device of claim 1, wherein the controller is further configured to:

determine an effective data retention time associated with the non-volatile memory array based at least in part on the difference.

5. The data storage device of claim 4, wherein the controller is further configured to determine the effective data retention time based at least in part on a program/erase cycling condition of a portion of the non-volatile memory array.

6. The data storage device of claim 1, wherein the controller is further configured to:

determine a shifted voltage read level associated with at least a portion of the non-volatile memory array based at least in part on the difference.

7. The data storage device of claim 1, wherein the controller is further configured to:

write three or more copies of the value to the non-volatile memory array;

read the three or more copies of the value from the non-volatile memory array; and

determine the number of bits of the written data programmed in the first logical state by identifying two or more matching read values of the three or more copies.

8. The data storage device of claim 1, wherein the controller is further configured to write the data to the non-volatile memory array using a multi-level cell (MLC) programming scheme including four programming states, wherein the data is programmed to cells of the non-volatile memory array comprising an upper bit and a lower bit of information.

9. The data storage device of claim 1, wherein the controller is further configured to write the value interleaved with dummy bits to reduce cell-to-cell interference.

10. A data storage device comprising:

a non-volatile memory array comprising a plurality of non-volatile memory devices; and

a controller configured to;

write data to a memory unit of the non-volatile memory array;

write a value to a memory indicating a number of bits of the written data programmed in a first of a plurality of logical states;

read the data from the non-volatile memory array;

determine a number of bits having the first of the logical states in the read data;

determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data;

determine a raw bit error rate (RBER) associated with at least a portion of the non-volatile memory array based at least in part on the difference; and

schedule a data refreshing operation for the at least a portion of the non-volatile memory array based at least in part on the RBER.

11. A data storage device comprising:

a non-volatile memory array comprising a plurality of non-volatile memory devices; and

a controller configured to;

write data to a memory unit of the non-volatile memory array using a multi-level cell (MLC) programming scheme including four programming states;

write a value to a memory indicating a number of cells programmed to a highest voltage state of the four programming states;

read the data from the non-volatile memory array;

determine a number of read cells of the highest voltage state;

read the value from the non-volatile memory array;

determine a difference between the number of programmed cells of the highest voltage state and the number of read cells of the highest voltage state;

determine one or more adjusted read levels associated with the non-volatile memory array based at least in part on the difference; and

schedule a data refreshing operation for at least a portion of the non-volatile memory array based at least in part on the difference.

12. The data storage device of claim 11, wherein the controller is further configured to determine the number of read cells of the highest voltage state at least in part by performing both upper page and lower page reads.

13. The data storage device of claim 11, wherein the controller is further configured to write the value using cells programmed to lowest or second-lowest programming states of the four programming states.

14. A method of managing data retention in a data storage system comprising a non-volatile memory array, the method comprising:

writing data to a memory unit of a non-volatile memory array;

writing a value to a memory indicating a number of bits of the written data programmed in a first of a plurality of logical states; and

writing multiple copies of the value to the non-volatile memory array;

reading the data from the non-volatile memory array;

determining a number of bits having the first of the logical states in the read data;

determining a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data; and

scheduling a data refreshing operation for at least a portion of the non-volatile memory array based at least in part on the difference,

wherein the method is performed under the control of a controller of the data storage system.

15. The method of claim 14, wherein the first of the plurality of logical states corresponds to a value of ‘

0’ and

a second of the plurality of logical states corresponds to a value of ‘

1’

.

16. The method of claim 14, wherein the first of the plurality of logical states corresponds to a value of ‘

1’ and

a second of the plurality of logical states corresponds to a value of ‘

0’

.

17. The method of claim 14, further comprising:

determining an effective data retention time associated with the non-volatile memory array based at least in part on the difference.

18. The method of claim 17, wherein determining the effective data retention time is based at least in part on a program/erase cycling condition of a portion of the non-volatile memory array.

19. The method of claim 14, further comprising:

determining a shifted voltage read level associated with at least a portion of the non-volatile memory array based at least in part on the difference.

20. The method of claim 14, wherein writing the multiple copies of the value to the non-volatile memory array comprises writing three or more copies of the value to the non-volatile memory array, and wherein the method further comprises:

reading the three or more copies of the value from the non-volatile memory array; and

determining the number of bits of the written data programmed in the first logical state by identifying two or more matching read values of the three or more copies.

21. The method of claim 14, wherein writing the data to the non-volatile memory array is performed according to a multi-level cell (MLC) programming scheme including four programming states, and wherein the data is programmed to cells of the non-volatile memory array comprising an upper bit and a lower bit of information.

22. The method of claim 14, further comprising writing dummy bits interleaved with the value to reduce cell-to-cell interference.

23. A method of managing data retention in a data storage system comprising a non-volatile memory array, the method comprising:

writing data to a memory unit of a non-volatile memory array;

writing a value to a memory indicating a number of bits of the written data programmed in a first of a plurality of logical states;

reading the data from the non-volatile memory array;

determining, from the data read from the non-volatile memory array, a number of read bits in the first of the plurality of logical states;

reading the value indicating the number of programmed bits from the memory;

determining a difference between the number of programmed bits and the number of read bits;

determining a raw bit error rate (RBER) associated with at least a portion of the non-volatile memory array based at least in part on the difference between the number of programmed bits and the number of read bits; and

scheduling a data refreshing operation for the at least a portion of the non-volatile memory array based at least in part on the RBER,

wherein the method is performed under the control of a controller of the data storage system.

24. A method of managing data retention in a data storage system comprising a non-volatile memory array, the method comprising:

writing data to a memory unit of a non-volatile memory array according to a multi-level cell (MLC) programming scheme including four programming states;

writing a value to a memory indicating a number of cells programmed to a highest voltage state of the four programming states;

reading the data from the non-volatile memory array;

determining a number of read cells of the highest voltage state;

reading the value from the non-volatile memory array;

determining a difference between the number of programmed cells of the highest voltage state and the number of read cells of the highest voltage state; and

determining one or more adjusted read levels associated with the non-volatile memory array based at least in part on the difference, and

scheduling a data refreshing operation for the at least a portion of the non-volatile memory array based at least in part on the difference.

25. The method of claim 24, further comprising determining the number of read cells of the highest voltage state at least in part by performing both upper page and lower page reads.

26. The method of claim 24, further comprising writing the value using cells programmed to lowest or second-lowest programming states of the four programming states.

27. A data storage device comprising:

a non-volatile memory array comprising a plurality of non-volatile memory devices; and

a controller configured to;

write data to a memory unit of the non-volatile memory array;

write multiple copies of a value to the non-volatile memory array, the value indicating a number of upper page bits of the written data programmed in a first of a plurality of logical states;

read the data from the memory array;

determine, based on the read data, a number of the upper page bits that have flipped;

determine a net difference between the number of upper page bits of the written data programmed in the first logical state and a number of upper page bits in the first logical state in the read data; and

schedule a data refreshing operation for the at least a portion of the non-volatile memory array based at least in part on the net difference.

28. The data storage device of claim 27, wherein the first of the plurality of logical states corresponds to a value of ‘

0’ and

a second of the plurality of logical states corresponds to a value of ‘

1’

.

29. The data storage device of claim 27, wherein the first of the plurality of logical states corresponds to a value of ‘

1’ and

a second of the plurality of logical states corresponds to a value of ‘

0’

.