Determining data retention time in a solid-state non-volatile memory
First Claim
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1. A method comprising:
- partitioning solid-state non-volatile memory cells of a non-volatile memory device into a plurality of units each individually allocatable for storage of user data;
allocating at least one of the plurality of units not storing user data as a control set;
storing user data from a host device to a first unit;
writing a test pattern to the control set;
reading the test pattern from the control set and identifying a total number of read errors;
determining a data retention time responsive to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern, the data retention time comprising an estimated time during which the memory device can store a set of data in a powered off condition and can successfully retrieve the data after being subsequently powered on;
obtaining system parameters comprising one or more of a current temperature value, a time stamp, a date stamp, and a total number of detected errors;
writing the parameters to the control set as a test log entry;
refreshing the user data in the first unit responsive to the determined data retention time; and
subsequently storing user data from the host device in the first unit.
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Abstract
Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.
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Citations
20 Claims
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1. A method comprising:
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partitioning solid-state non-volatile memory cells of a non-volatile memory device into a plurality of units each individually allocatable for storage of user data; allocating at least one of the plurality of units not storing user data as a control set; storing user data from a host device to a first unit; writing a test pattern to the control set; reading the test pattern from the control set and identifying a total number of read errors; determining a data retention time responsive to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern, the data retention time comprising an estimated time during which the memory device can store a set of data in a powered off condition and can successfully retrieve the data after being subsequently powered on; obtaining system parameters comprising one or more of a current temperature value, a time stamp, a date stamp, and a total number of detected errors; writing the parameters to the control set as a test log entry; refreshing the user data in the first unit responsive to the determined data retention time; and subsequently storing user data from the host device in the first unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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an array of solid-state non-volatile memory cells arranged into addressable blocks; a control circuit configured to direct storage of user data received from a host device to a first addressable block and to allocate at least one addressable block not storing user data as a control set; an evaluation circuit configured to write a test pattern to the control set, subsequently read the test pattern from the control set, identify a total number of read errors in the subsequently read test pattern, and determine a data retention time responsive to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern, the elapsed time interval comprising an elapsed duration of time of at least 30 minutes without an application of an intervening refresh operation to the memory cells during said interval; obtain system parameters comprising one or more of a current temperature value, a time stamp, a date stamp, and a total number of detected errors; and write the parameters to the control set as a test log entry; the control circuit further configured to refresh the user data previously stored in the first addressable block responsive to the determined data retention time. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An apparatus comprising:
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a flash memory array arranged into a plurality of garbage collection units (GCUs) erased and allocated as a unit; a control circuit configured to direct storage of user data from a host device into a first GCU; and an evaluation circuit which determines a current data retention time of the flash memory array by storing a test pattern in a second GCU during continued storage of the data in the first GCU and, at the conclusion of an elapsed time interval, identifies a total number of errors in a copy of the test pattern read back from the second GCU; the control circuit further configured to obtain system parameters comprising one or more of a current temperature value, a time stamp, a date stamp, and a total number of detected errors; write the parameters to the control set as a test log entry; and communicate the current data retention time to a host device and to subsequently direct storage of user data from the host device to the second GCU. - View Dependent Claims (19, 20)
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Specification