Method of fabricating semiconductor patterns

• US 9,263,282 B2
• Filed: 06/13/2013
• Issued: 02/16/2016
• Est. Priority Date: 06/13/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chin-Fu, Liu, Chih-Chien, Hsu, Chia-Lin, Chien, Chin-Cheng, Wu, Chun-Yuan
• Primary Examiner(s): Au, Bac
• Application Number:
  US13/916,584
• Publication Number:
  US 20140370701A1
• Time in Patent Office: 978 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin

Abstract

A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Claims

1. A method of fabricating semiconductor patterns, comprising steps as follows:

providing a substrate, wherein the substrate comprises a silicon layer formed thereon and a protection layer formed atop the silicon layer;

forming a dummy structure on the protection layer,

forming a spacer layer on a sidewall of the dummy structure with a semiconductor material;

removing the dummy structure;

forming at least a first semiconductor pattern and at least a second semiconductor pattern with the spacer layer on the protection layer, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern;

forming a barrier pattern over a surface of the first semiconductor pattern, and exposing the second semiconductor pattern;

forming a sacrificial structure layer by reacting a surface portion of the second semiconductor pattern; and

removing the barrier pattern and the sacrificial structure layer to obtain the line width of the second semiconductor pattern configured to be less than the line width of the first semiconductor pattern.

2. The method of fabricating semiconductor patterns according to claim 1, wherein a material for forming the protection layer has an etching selectivity with respect to a material for forming the dummy structure, a material for forming the barrier pattern or a material of the sacrificial structure layer.

3. The method of fabricating semiconductor patterns according to claim 2, wherein the material for forming the protection layer is silicon nitride, the material for forming the dummy structure and the barrier pattern is silicon oxide, and the material of sacrificial layer is silicon oxide.

4. The method of fabricating semiconductor patterns according to claim 1, further comprising steps as follows:

patterning the protection layer and the silicon layer with the first semiconductor pattern and the second semiconductor pattern acting as a patterned mask to form a first silicon pattern and a second silicon pattern, wherein a line width of the second silicon pattern is less than a line width of the first silicon pattern;

forming an insulation layer over the first silicon pattern and the second silicon pattern, then polishing the insulation layer;

etching back a portion of the insulation layer to expose a portion of the surface of the first silicon pattern and a portion of the surface of the second silicon pattern;

forming a gate dielectric layer on the exposed portion of the surface of the first silicon pattern and the exposed portion of the surface of the second silicon pattern; and

forming a metal gate on the gate dielectric layer.

5. The method of fabricating semiconductor patterns according to claim 4, wherein the line width of the first silicon pattern and the line width of the second silicon pattern are not greater than 50 nanometers.

6. The method of fabricating semiconductor patterns according to claim 1, wherein the step of forming the barrier pattern over the surface of the first semiconductor pattern comprises sub-steps as follows:

forming a first material layer over the first semiconductor pattern and the second semiconductor pattern by performing an atomic layer deposition process; and

forming a mask above the first semiconductor pattern, then removing a portion of the first material layer to expose the second semiconductor pattern.

7. The method of fabricating semiconductor patterns according to claim 6, a material for forming the barrier pattern is selected from oxide, nitride, oxynitride or carbide.

8. The method of fabricating semiconductor patterns according to claim 6, wherein a material for forming the mask is a photo resist.

9. The method of fabricating semiconductor patterns according to claim 6, wherein a material for forming the first material layer is an oxide, the surface portion of the second semiconductor pattern is reacted with an oxidant for use in removing the mask to form the sacrificial structure layer, and the first material layer and the sacrificial structure layer are removed with an etching formula.

10. The method of fabricating semiconductor patterns according to claim 1, wherein the step of forming the sacrificial structure layer by reacting the surface portion of the second semiconductor pattern comprises performing an oxidation, a nitridation, an oxynitridation or a carbonation reaction, and the sacrificial structure layer and the barrier pattern are removed with an etching formula.

11. The method of fabricating semiconductor patterns according to claim 1, wherein the substrate further has at least a third semiconductor pattern formed thereon, a line width of the third semiconductor pattern is identical to the line width of the first semiconductor pattern, after the barrier pattern is formed over the first semiconductor pattern and the third semiconductor pattern, then the second semiconductor pattern is exposed, and the barrier pattern and the sacrificial structure layer are removed, the method further comprises steps as follows:

forming a second barrier pattern over a surface of the third semiconductor pattern, then exposing the first semiconductor pattern and the second semiconductor pattern;

forming a second sacrificial structure layer by reacting a surface portion of the first semiconductor pattern and a surface portion of the second semiconductor pattern; and

removing the second barrier pattern and the second sacrificial structure layer to obtain the line width of the second semiconductor pattern configured to be less than the line width of the first semiconductor pattern and the line width of the first semiconductor pattern configured to be less than the line width of the third semiconductor pattern.

12. The method of fabricating semiconductor patterns according to claim 11, wherein a material for forming the second barrier pattern is selected from oxide, nitride, oxynitride or carbide.

13. The method of fabricating semiconductor patterns according to claim 11, wherein the step of forming the second sacrificial structure layer by reacting the surface portion of the second semiconductor pattern comprises performing an oxidation, a nitridation, an oxynitridation or a carbonation reaction, and the second sacrificial structure layer and the second barrier pattern are removed with an etching formula.