Decoupling MIM capacitor designs for interposers and methods of manufacture thereof

• US 9,263,415 B2
• Filed: 04/29/2014
• Issued: 02/16/2016
• Est. Priority Date: 08/12/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tzeng, Kuo-Chyuan, Tu, Kuo-Chi, Wang, Chen-Jong, Lee, Hsiang-Fan
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US14/265,223
• Publication Number:
  US 20140235019A1
• Time in Patent Office: 658 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

Claims

1. A method for forming a semiconductor device, the method comprising:

providing an interposer, the interposer having a first plurality of contact pads and a second plurality of contact pads, the interposer having a decoupling metal-insulator-metal (MIM) capacitor formed thereon, wherein the decoupling MIM capacitor comprises a bottom electrode, a capacitor dielectric over the bottom electrode, and a top electrode over the capacitor dielectric, wherein the interposer comprises a bottom plate pick-up, the bottom plate pick-up being interposed between the bottom electrode and a substrate of the interposer; and

mounting an integrated circuit die to the second plurality of contact pads, the decoupling MIM capacitor being electrically interposed between the integrated circuit die and a first contact pad of the first plurality of contact pads.

2. The method of claim 1, wherein the interposer is free from active circuitry.

3. The method of claim 1, wherein the top electrode comprises a first top electrode material and a second top electrode material over the first top electrode material, the first top electrode material being different from the second top electrode material.

4. The method of claim 1, wherein the capacitor dielectric has a first plurality of portions parallel to a top surface of the interposer and a second plurality of portions perpendicular to the top surface of the interposer.

5. The method of claim 1, wherein the interposer comprises a top plate pick-up, the top plate pick-up being coupled to the top electrode using a via.

6. The method of claim 1, wherein the interposer comprises a top plate pick-up, the top plate pick-up being formed in a same metallization layer as the top electrode.

7. The method of claim 1, wherein the bottom electrode is formed along sidewalls and a bottom of a recess formed in a dielectric layer.

8. A method for forming a semiconductor device, the method comprising:

providing an interposer, the interposer comprising;

a first contact pad on a first side of the interposer and a second contact pad on a second side of the interposer, the first contact pad being electrically coupled to the second contact pad; and

a decoupling metal-insulator-metal (MIM) capacitor, the decoupling MIM capacitor being electrically coupled between the first contact pad and the second contact pad, wherein the decoupling MIM capacitor comprises a bottom electrode, a capacitor dielectric over the bottom electrode, and a top electrode over the capacitor dielectric; and

electrically coupling an integrated circuit die to the first contact pad on the interposer;

wherein the decoupling MIM capacitor is formed at least in part by forming one or more trenches in one or more metallization layers of the interposer, forming the bottom electrode along sidewalls and bottoms of the one or more trenches.

9. The method of claim 8, wherein the interposer is free from active circuitry.

10. The method of claim 8, wherein the decoupling MIM capacitor is formed by forming the capacitor dielectric over the bottom electrode and a topmost surface of the one or more metallization layers, and forming the top electrode over the capacitor dielectric, the top electrode conforming to a shape of the capacitor dielectric.

11. The method of claim 8, wherein the top electrode comprises a first top electrode material and a second top electrode material over the first top electrode material, the first top electrode material being different from the second top electrode material.

12. The method of claim 8, wherein the top electrode has a first portion having a first width and a second portion having a second width, the first width being larger than the second width.

13. The method of claim 8, further comprising forming a top plate pick-up in a first metallization layer of the interposer and forming the top electrode in a second metallization layer of the interposer, wherein the first metallization layer is different from the second metallization layer, and wherein the top electrode is coupled to the top plate pick-up using a via.

14. The method of claim 8, wherein the capacitor dielectric has a first plurality of portions parallel to the first side of the interposer and a second plurality of portions perpendicular to the first side of the interposer.

15. A method for forming a semiconductor device, the method comprising:

providing an interposer, the interposer comprising;

a substrate;

one or more metallization layers over the substrate;

a decoupling metal-insulator-metal (MIM) capacitor in the one or more metallization layers, the decoupling MIM capacitor having a first electrode, a second electrode, and a dielectric layer interposed between the first electrode and the second electrode;

a first contact pad electrically coupled to the first electrode; and

a second contact pad electrically coupled to the second electrode; and

electrically coupling an integrated circuit die to the first contact pad.

16. The method of claim 15, wherein the dielectric layer has a first portion parallel to a topmost surface of the substrate and a second portion perpendicular to the topmost surface of the substrate.

17. The method of claim 15, wherein the first electrode comprises a first electrode material and a second electrode material over the first electrode material, the first electrode material being different from the second electrode material.

18. The method of claim 15, further comprising disposing a molding compound over the integrated circuit die and the interposer.

19. The method of claim 15, wherein the interposer comprises a top plate pick-up in the one or more metallization layers, the top plate pick-up being coupled to the first electrode, a topmost surface of the top plate pick-up being higher than a topmost surface of the first electrode and a bottommost surface of the top plate pick-up being lower than a bottommost surface of the first electrode.

20. The method of claim 15, wherein the interposer comprises a top plate pick-up in the one or more metallization layers, the top plate pick-up being coupled to the first electrode using a via.