Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines

• US 9,263,455 B2
• Filed: 07/23/2013
• Issued: 02/16/2016
• Est. Priority Date: 07/23/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Karda, Kamal M., Mueller, Wolfgang, Dhir, Sourabh, Kerr, Robert, Hwang, Sangmin, Liu, Haitao
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US13/948,746
• Publication Number:
  US 20150028406A1
• Time in Patent Office: 938 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1436 Dynamic random-access memory [DRAM]
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Claims

1. A method of forming an array of recessed access gate lines, comprising:

etching isolation trenches into semiconductor material to a first depth to define active area regions;

etching the isolation trenches deeper into the semiconductor material to a second depth, the etching to the second depth projecting the isolation trenches longitudinally into opposing longitudinal ends of individual active area regions below the first depth;

forming dielectric trench isolation material in the extended isolation trenches including projecting portions thereof to form dielectric projections extending into the opposing longitudinal ends of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions, the semiconductor material being elevationally over the dielectric projections; and

forming recessed access gate lines which individually extend transversally across the active area regions and extend between the longitudinal ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material.

2. The method of claim 1 wherein the deeper etching does not project the isolation trenches into opposing sides of the individual active area regions longitudinally along all of the individual active area regions below the first depth.

3. The method of claim 1 wherein the deeper etching projects the isolation trenches into opposing sides of the individual active area regions longitudinally along all of the individual active area regions below the first depth.

4. The method of claim 1 wherein the deeper etching comprises:

forming masking material over sidewalls and bases of the isolation trenches that have been etched to the first depth, the masking material being thicker centrally over the isolation trench bases that are between immediately side-to-side adjacent active area regions than centrally over the isolation trench bases that are between immediately end-to-end adjacent active area regions;

etching the masking material to centrally expose the isolation trench bases that are between immediately end-to-end adjacent active area regions but not expose the isolation trench bases that are centrally between immediately side-to-side adjacent active area regions;

first etching the semiconductor material to project the isolation trenches longitudinally into opposing longitudinal ends of individual active area regions below the first depth;

after the first etching, removing all of the masking material from the isolation trenches; and

after the removing, second etching the semiconductor material to the second depth.

5. A method of forming an array of conductive lines, comprising:

etching isolation trenches into semiconductor material to a first depth to define active area regions;

etching the isolation trenches deeper into the semiconductor material to a second depth, the etching to the second depth projecting the isolation trenches laterally into opposing sides of individual active area regions below the first depth;

forming dielectric trench isolation material in the extended isolation trenches including projecting portions thereof to form dielectric projections extending laterally into the opposing sides of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions, the semiconductor material being elevationally over the dielectric projections;

etching a contact opening into the semiconductor material at a longitudinally central portion of the individual active area regions to form a longitudinally central semiconductor material elevationally outer surface that is elevationally inward relative to the elevationally outermost surface of the semiconductor material in the individual active area regions; and

forming conductive lines that individually extend transversally across and elevationally over the longitudinally central portions of the active area regions, conductive material being directly against the longitudinally central semiconductor material elevationally outer surface of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover.

6. The method of claim 5 comprising, prior to etching the contact openings, forming recessed access gate lines which individually extend transversally across the active area regions and extend between the longitudinal ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material.

7. A method of forming an array of recessed access gate lines and an array of conductive lines, comprising:

etching isolation trenches into semiconductor material to a first depth to define active area regions;

etching the isolation trenches deeper into the semiconductor material to a second depth, the etching to the second depth projecting the isolation trenches longitudinally into opposing longitudinal ends of individual active area regions below the first depth and projecting the isolation trenches laterally into opposing sides of the individual active area regions below the first depth;

forming dielectric trench isolation material in the extended isolation trenches including projecting portions thereof to form dielectric end projections extending into the opposing longitudinal ends of the individual active area regions under an elevationally outermost surface of the semiconductor material of the active area regions and to form dielectric lateral projections extending laterally into the opposing sides of the individual active area regions under the elevationally outermost surface of the semiconductor material of the active area regions, the semiconductor material being elevationally over the longitudinal end and lateral dielectric projections;

forming recessed access gate lines which individually extend transversally across the active area regions and extend between the longitudinal ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material;

after forming the recessed access gate lines, etching a contact opening into the semiconductor material at a longitudinally central portion of the individual active area regions to form a longitudinally central semiconductor material elevationally outer surface that is elevationally inward relative to the elevationally outermost surface of the semiconductor material in the individual active area regions; and

forming conductive lines that individually extend transversally across and elevationally over the longitudinally central portions of the active area regions, conductive material being directly against the longitudinally central semiconductor material elevationally outer surface of the individual active area regions and being conductively coupled to the conductive line transversally crossing thereover.