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Cross-coupling of gate conductor line and active region in semiconductor devices

  • US 9,263,457 B2
  • Filed: 01/02/2014
  • Issued: 02/16/2016
  • Est. Priority Date: 08/10/2011
  • Status: Active Grant
First Claim
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1. A method of forming a semiconductor structure comprising:

  • forming a gate cavity by removing a disposable gate structure selective to a planarization dielectric layer on a semiconductor substrate, wherein at least one surface of at least one active region and a portion of a shallow trench isolation structure are exposed within said gate cavity, wherein said at least one active region includes a first active region and a second active region that are laterally spaced by the shallow trench isolation structure;

    depositing a gate dielectric layer within said gate cavity on said exposed portion of the shallow trench isolation structure and on said exposed at least one surface of the at least one active region;

    removing a portion of said gate dielectric layer within said gate cavity from above said shallow isolation trench and another portion of said gate dielectric layer within said gate cavity from above one of said at least one active region, and implanting electrical dopant into an area of said semiconductor substrate from which the another portion of the said gate dielectric layer is removed; and

    filling said gate cavity with a conductive material and planarizing said conductive material to form a gate conductor, wherein the gate conductor contacts a gate dielectric, which is a remaining portion of said gate dielectric layer.

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