Cross-coupling of gate conductor line and active region in semiconductor devices

• US 9,263,457 B2
• Filed: 01/02/2014
• Issued: 02/16/2016
• Est. Priority Date: 08/10/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Sardesai, Viraj Y., Wong, Robert C.
• Primary Examiner(s): Moore, Whitney T
• Assistant Examiner(s): Wilson, Scott R
• Application Number:
  US14/146,063
• Publication Number:
  US 20140113417A1
• Time in Patent Office: 775 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.

Claims

1. A method of forming a semiconductor structure comprising:

forming a gate cavity by removing a disposable gate structure selective to a planarization dielectric layer on a semiconductor substrate, wherein at least one surface of at least one active region and a portion of a shallow trench isolation structure are exposed within said gate cavity, wherein said at least one active region includes a first active region and a second active region that are laterally spaced by the shallow trench isolation structure;

depositing a gate dielectric layer within said gate cavity on said exposed portion of the shallow trench isolation structure and on said exposed at least one surface of the at least one active region;

removing a portion of said gate dielectric layer within said gate cavity from above said shallow isolation trench and another portion of said gate dielectric layer within said gate cavity from above one of said at least one active region, and implanting electrical dopant into an area of said semiconductor substrate from which the another portion of the said gate dielectric layer is removed; and

filling said gate cavity with a conductive material and planarizing said conductive material to form a gate conductor, wherein the gate conductor contacts a gate dielectric, which is a remaining portion of said gate dielectric layer.

2. The method of claim 1, wherein said gate conductor fills an opening in the gate dielectric layer formed by the removing of the portion of said gate dielectric layer within said gate cavity from above said shallow isolation trench and the another portion of said gate dielectric layer within said gate cavity from above one of said at least one active region, and wherein said gate conductor contacts a semiconductor surface of said one of said at least one active region through the opening in the gate dielectric layer.

3. The method of claim 1, wherein said gate conductor is vertically spaced from said first active region by said gate dielectric and said semiconductor surface is a surface of said second active region.

4. The method of claim 1, wherein said portion of said gate dielectric layer and said another portion of said gate dielectric layer are is removed by:

applying and lithographically patterning a photoresist over said gate dielectric layer; and

etching said portion of said gate dielectric layer and said another portion of said gate dielectric layer which are exposed to etchants within said gate cavity, and a non-etched portion of said gate dielectric layer within said gate cavity is covered by said photoresist.

5. The method of claim 1, wherein said disposable gate structure is formed on said semiconductor substrate before depositing said planarization dielectric layer, and a top surface of said planarization dielectric layer is planarized before forming said gate cavity.

6. The method of claim 1, wherein said removed portion of said gate dielectric layer from above one of said at least one active region overlies a portion of said second active region and does not overlie any portion of said first active region.

7. The method of claim 1, wherein said semiconductor structure comprises a static random access memory (SRAM) cell, and an end portion of said gate conductor contacts a drain region of a field effect transistor.

8. A method of forming a semiconductor structure comprising:

forming a gate dielectric layer over at least one active region in a semiconductor substrate, wherein said at least one active region includes a first active region and a second active region that are laterally spaced by a shallow trench isolation structure;

removing a portion of said gate dielectric layer from above said shallow isolation trench and another portion of said gate dielectric layer from above one of said at least one active region, and implanting electrical dopant into an area of said semiconductor substrate from which the another portion of the said gate dielectric layer is removed; and

depositing and patterning a conductive material layer to form a gate conductor, wherein said gate conductor contacts a gate dielectric, which is a remaining portion of said gate dielectric layer, and a semiconductor surface of said one of said at least one active region.

9. The method of claim 8, wherein said gate conductor is vertically spaced from said first active region by said gate dielectric and said semiconductor surface is a surface of said second active region.

10. The method of claim 8, wherein said gate dielectric layer is deposited on all top surfaces of said at least one active region and said shallow trench isolation structure.

11. The method of claim 8, wherein said removed portion of said gate dielectric layer from above one of said at least one active region overlies a portion of said second active region and does not overlie any portion of said first active region.

12. The method of claim 8, wherein said semiconductor structure comprises a static random access memory (SRAM) cell, and an end portion of said gate conductor contacts a drain region of a field effect transistor.