Advanced transistors with punch through suppression

• US 9,263,523 B2
• Filed: 02/24/2014
• Issued: 02/16/2016
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Shifren, Lucian, Ranade, Pushkar, Gregory, Paul E., Sonkusale, Sachin R., Zhang, Weimin, Thompson, Scott E.
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US14/188,218
• Publication Number:
  US 20140167156A1
• Time in Patent Office: 722 Days
• Field of Search: 257/336, 257/337
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10¹⁸ dopant atoms per cm³. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Claims

1. A die, comprising:

a substrate that is a single crystal of semiconductor material;

a plurality of field effect transistor structures supported by the substrate each having a gate, a source, and a drain;

wherein at least one of the transistor structures has a plurality of distinct doped regions underlying the gate and extending between the source and drain, the plurality of doped regions implanted to define a dopant profile of p-type or n-type material for the at least one of the transistor structures, the dopant profile having a peak dopant concentration at a first depth from the gate, a first intermediate dopant concentration at a second depth from the gate, the first intermediate dopant concentration being lower than the peak dopant concentration;

wherein each of the plurality of transistor structures includes a channel region commonly formed by an undoped blanket epitaxial growth, the channel region being directly on a threshold voltage control region formed in the single crystal of the single semiconductor material, the threshold voltage control region associated with the first intermediate dopant concentration.

2. The die of claim 1, wherein the dopant profile includes a second intermediate dopant concentration at a third depth from the gate, the second intermediate dopant concentration is higher than the first intermediate dopant concentration.

3. The die of claim 2, wherein the dopant profile has a second dopant concentration at a second point between the first depth and the third depth, the second dopant concentration being less than or equal to the second intermediate dopant concentration to establish a second notch in the dopant profile.

4. The die of claim 2, wherein the second intermediate dopant concentration is associated with a suppression of punch through region of at least one of the transistor structures.

5. The die of claim 2, wherein the third depth is deeper below the gate than the first depth.

6. The die of claim 1, wherein the peak dopant concentration at the first depth sets a depletion depth for the at least one of the transistor structures when a voltage is applied to the gate.

7. The die of claim 1, further comprising:

a bias structure coupled to the source of the at least one of the transistor structures, the bias structure operable to modify an operational threshold voltage of the at least one of the transistor structures.

8. The die of claim 7, further comprising:

a fixed voltage source coupled to the bias structure to statically set the threshold voltage of the at least one of the transistor structures.

9. The die of claim 7, further comprising:

a variable voltage source coupled to the bias structure to dynamically adjust the threshold voltage of the at least one of the transistor structures.

10. The die of claim 7, wherein the plurality of transistor structures are separated into different bias sections, a first bias section providing no threshold voltage adjustment, a second bias section operable to provide static threshold voltage adjustment, and a third bias section operable to provide dynamic threshold voltage adjustment.

11. The die of claim 10, wherein the different bias sections have different threshold voltages with or without any adjustment.

12. The die of claim 1, wherein the first depth is deeper below the gate than the second depth.

13. The die of claim 1, wherein the first depth is in a range between one half and one fifth of a length of the gate.

14. The die of claim 1, wherein the plurality of doped regions are formed in the substrate.

15. The die of claim 1, wherein the plurality of doped regions are formed on the substrate.

16. The die of claim 1, further comprising:

source and drain extensions extending into the channel of the at least one of the transistor structures.

17. The die of claim 1, wherein the plurality of doped regions are in contact with the source and drain.

18. The die of claim 1, wherein the dopant profile has a first dopant concentration at a first point between the first depth and the second depth, the first dopant concentration being less than or equal to the first intermediate dopant concentration to establish a first notch in the dopant profile.