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Advanced transistors with punch through suppression

  • US 9,263,523 B2
  • Filed: 02/24/2014
  • Issued: 02/16/2016
  • Est. Priority Date: 09/30/2009
  • Status: Active Grant
First Claim
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1. A die, comprising:

  • a substrate that is a single crystal of semiconductor material;

    a plurality of field effect transistor structures supported by the substrate each having a gate, a source, and a drain;

    wherein at least one of the transistor structures has a plurality of distinct doped regions underlying the gate and extending between the source and drain, the plurality of doped regions implanted to define a dopant profile of p-type or n-type material for the at least one of the transistor structures, the dopant profile having a peak dopant concentration at a first depth from the gate, a first intermediate dopant concentration at a second depth from the gate, the first intermediate dopant concentration being lower than the peak dopant concentration;

    wherein each of the plurality of transistor structures includes a channel region commonly formed by an undoped blanket epitaxial growth, the channel region being directly on a threshold voltage control region formed in the single crystal of the single semiconductor material, the threshold voltage control region associated with the first intermediate dopant concentration.

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