MOS-transistor with separated electrodes arranged in a trench

• US 9,263,552 B2
• Filed: 06/05/2014
• Issued: 02/16/2016
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Vellei, Antonio
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Yi, Changhyun
• Application Number:
  US14/296,605
• Publication Number:
  US 20150357437A1
• Time in Patent Office: 621 Days
• Field of Search: 257/329, 257/331, 257/341, 438/268
• US Class Current: 1/1
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOS transistor is produced by forming a first trench in a semiconductor body, forming a first isolation layer on inner surfaces of the first trench, and filling the first trench with conductive material to form a first electrode within the first trench. A portion of the first electrode is removed along one side wall of the first trench to form a cavity located within the first trench. A second isolation layer is formed on inner surfaces of the cavity, and the cavity is at least partially filled with conductive material to form a second electrode within the cavity. A structured third isolation layer is formed on a top surface of the semiconductor body, and a metallization layer is formed on the structured third isolation layer. The first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer.

Claims

1. A method for producing a trench transistor, the method comprising:

providing a semiconductor body;

forming a first trench in the semiconductor body, the first trench comprising two side walls and a bottom surface;

forming a first isolation layer on inner surfaces of the first trench;

filling the first trench with conductive material to form a first electrode within the first trench;

removing a portion of the first electrode along one of the side walls of the first trench to form a cavity in the first electrode, the cavity being located within the first trench;

forming a second isolation layer on inner surfaces of the cavity;

at least partially filling the cavity with conductive material to form a second electrode within the cavity;

forming a structured third isolation layer on a top surface of the semiconductor body; and

forming a metallization layer on the structured third isolation layer, wherein the first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer.

2. The method of claim 1, further comprising:

forming a body zone in the semiconductor body, the body zone adjoining a side wall of the first trench; and

forming a source zone in the semiconductor body, the source zone adjoining a top surface of the semiconductor body and the side wall of the first trench.

3. The method of claim 2, wherein the source zone is electrically coupled to the metallization layer via openings in the structured third isolation layer.

4. The method of claim 1, wherein a side wall of the cavity is substantially vertical and coplanar with a corresponding side wall of the first trench.

5. The method of claim 1, wherein a horizontal width of the cavity is less than a horizontal width of the first trench.

6. The method of claim 5, wherein a vertical depth of the cavity is less or equal then a depth of the first trench, the vertical depth of the cavity being measured between a top surface of the first electrode and a bottom side of the cavity.

7. The method of claim 5, wherein a vertical depth of the cavity is greater than a depth of the first trench, the vertical depth of the cavity being measured between a top surface of the first electrode and a bottom side of the cavity.

8. The method of claim 1, wherein at least one of the first, the second and the third isolation layers is an oxide layer.

9. The method of claim 1, wherein the cavity is only partially filled with the conductive material to form the second electrode within the cavity, and a third electrode is formed in the cavity vertically above the second electrode and isolated from the second electrode.

10. The method of claim 1, further comprising:

removing a further portion of the first electrode to form a further cavity in the first electrode, the further cavity being located within the first trench;

forming an further isolation layer on inner surfaces of the further cavity; and

at least partially filling the further cavity with conductive material to form a further electrode within the further cavity.

11. The method of claim 1, wherein the first trench and the cavity are formed using photolithography and etching.

12. The method of claim 1, wherein the first, second and third isolation layers are each formed by thermal oxide generation and/or oxide deposition.

13. The method of claim 1, wherein the second isolation layer lines each of the inner surfaces of the cavity when the cavity is at least partially filled with conductive material such that the second electrode is completely electrically insulated from the semiconductor body by the second isolation layer.

14. A method for producing a trench transistor, the method comprising:

providing a semiconductor body;

forming a first trench in the semiconductor body;

forming a first isolation layer on inner surfaces of the first trench;

filling the first trench with conductive material to form a first electrode within the first trench;

forming a second trench in the semiconductor body directly adjoining the first trench, wherein forming the second trench comprises exposing a side surface of the first electrode or the first isolation layer, the side surface of the first electrode or the first isolation layer extending between a main lateral surface of the semiconductor body and a bottom of the first trench;

forming a second isolation layer on inner surfaces of the second trench;

at least partially filling second trench with conductive material to form a second electrode within the second trench;

forming a structured third isolation layer on a top surface of the semiconductor body; and

forming a metallization layer on the structured third isolation layer, wherein the first or the second electrode is electrically and thermally connected to the metallization layer via openings in the structured third isolation layer.

15. The method of claim 14, further comprising:

forming a body zone in the semiconductor body, the body zone adjoining a side wall of the first trench; and

forming a source zone in the semiconductor body, the source zone adjoining a top surface of the semiconductor body and the side wall of the first trench.

16. The method of claim 15, wherein the source zone is electrically coupled to the metallization layer via openings in the structured third isolation layer.

17. The method of claim 14, wherein a side wall of the second trench is substantially vertical and aligned with an adjoining side wall of the first trench.

18. The method of claim 14, wherein the first and the second trenches overlap in a lateral direction.

19. The method of claim 14, wherein a horizontal width of the second trench is less than or equal to a horizontal width of the first trench.

20. The method of claim 14, wherein a vertical depth of the second trench is less than or equal to a depth of the first trench, the vertical depth of the second trench being measured between a top surface of the first electrode and a bottom side of the second trench.

21. The method of claim 14, wherein a vertical depth of the second trench is greater than a depth of the first trench, the vertical depth of the second trench being measured between a top surface of the first electrode and a bottom side of the second trench.

22. The method of claim 14, wherein the first and the second trenches are formed using photolithography and etching.

23. The method of claim 14, wherein the first, second and third isolation layers are each formed by thermal oxide generation and/or oxide deposition.

24. The method of claim 14, wherein the second isolation layer lines each of the inner surfaces of the second trench when the second trench is at least partially filled with conductive material such that the second electrode is completely electrically insulated from the semiconductor body by the second isolation layer.