Semiconductor device with bottom gate wirings

• US 9,263,572 B2
• Filed: 09/19/2014
• Issued: 02/16/2016
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Sanken Electric Company Limited
• Original Assignee: Sanken Electric Company Limited
• Inventors: Kawashiri, Satoshi, Torii, Katsuyuki
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US14/491,168
• Publication Number:
  US 20150084123A1
• Time in Patent Office: 515 Days
• Field of Search: 257/330
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.

Claims

1. A semiconductor device comprising:

a first semiconductor region, which has a first conductivity type;

a second semiconductor region, which has a second conductivity type and is arranged on the first semiconductor region;

a third semiconductor region, which has the first conductivity type and is arranged on the second semiconductor region;

a fourth semiconductor region, which has the second conductivity type and is arranged on the third semiconductor region;

an insulation film, which is arranged on an inner wall of a recess extending from an upper surface of the fourth semiconductor region and penetrate the fourth semiconductor region and the third semiconductor region to reach the second semiconductor region;

a control electrode, which is arranged on a region of the insulation film on a side surface of the recess, the region facing a side surface of the third semiconductor region;

a first main electrode, which is electrically connected to the first semiconductor region;

a second main electrode, which is electrically connected to the fourth semiconductor region; and

a bottom electrode, which is arranged on the insulation film with being separated from the control electrode on a bottom surface of the recess and is electrically connected to the second main electrode,

wherein a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses, as viewed from a plan view,

wherein a plurality of the recesses is formed in a lattice shape to intersect with each other,

wherein pillars, which corresponds areas formed in an island shape surrounded by the recesses, are two-dimensionally arranged, as viewed from a plan view,

wherein gate electrodes formed on side faces of the two adjacent pillars are connected by a bottom gate wiring, which is formed on the oxide film at a bottom surface of the recess between the two adjacent pillars, and

wherein a bottom electrode separated from the control electrode and electrically connected to the first main electrode is provided on the oxide film of the bottom surface of the recess between the two adjacent bottom gate wirings.

2. The semiconductor device according to claim 1,

wherein the gate electrodes formed on the side surfaces of the two pillars adjacent to each other in one direction are connected by the bottom gate wiring extending in the one direction.

3. The semiconductor device according to claim 2,

wherein the gate electrodes formed on the side surfaces of the two pillars adjacent to each other in two intersecting directions are connected by the bottom gate wirings extending in the intersecting directions.

4. The semiconductor device according to claim 1,

wherein a total area of the pillars is smaller than a sum of a total area of the bottom electrodes and a total area of the bottom gate wirings, when seen from a plan view.