Method for forming thermoelectric element using electrolytic etching

• US 9,263,662 B2
• Filed: 03/24/2015
• Issued: 02/16/2016
• Est. Priority Date: 03/25/2014
• Status: Expired due to Fees

• Current Assignee: Matrix Industries, Inc.
• Original Assignee: Silicium Energy, Inc.
• Inventors: Boukai, Akram I., Tham, Douglas W., Liang, Haifan
• Primary Examiner(s): Jung, Michael
• Application Number:
  US14/667,177
• Publication Number:
  US 20150280099A1
• Time in Patent Office: 329 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H10N 10/01 Manufacture or treatment
• CPC Class Codes: H10N 10/17 characterised by the structure or configuration of the cell or thermocouple forming the device
• CPC Class Codes: H10N 10/855 comprising compounds containing boron, carbon, oxygen or nitrogen
• CPC Class Codes: H10N 10/8556 comprising compounds containing germanium or silicon

Abstract

The present disclosure provides a thermoelectric element comprising a flexible semiconductor substrate having exposed surfaces with a metal content that is less than about 1% as measured by x-ray photoelectron spectroscopy (XPS) and a figure of merit (ZT) that is at least about 0.25, wherein the flexible semiconductor substrate has a Young'"'"'s Modulus that is less than or equal to about 1×10⁶ pounds per square inch (psi) at 25° C.

Claims

1. A method for forming a thermoelectric element having a figure of merit (ZT) that is at least 0.25 at 25°

C., comprising;

(a) providing a reaction space comprising a semiconductor substrate, a working electrode in electrical communication with a first surface of said semiconductor substrate, an etching solution in contact with a second surface of said semiconductor substrate, and a counter electrode in said etching solution, wherein said first and second surfaces of said semiconductor substrate is substantially free of a metallic coating; and

(b) using said working electrode and said counter electrode to (i) direct electrical current to said semiconductor substrate at a current density of at least 0.1 mA/cm², and (ii) etch said second surface of said semiconductor substrate with said etching solution to form a pattern of holes in said semiconductor substrate, thereby forming said thermoelectric element having said ZT that is at least 0.25,

wherein said etch is performed at an electrical potential of at least 1 volt (V) across said semiconductor substrate and said etching solution, and

wherein said etch has an etch rate that is at least 1 nanometer (nm) per second at 25°

C.

2. The method of claim 1, wherein said etch rate is at least 100 nm per second.

3. The method of claim 1, wherein said current density is at least 10 mA/cm².

4. The method of claim 3, wherein said current density is less than or equal to 50 mA/cm².

5. The method of claim 1, further comprising, prior to (b), heating said etching solution to a temperature that is greater than 25°

C.

6. The method of claim 1, wherein said semiconductor substrate is etched in the absence of a metal catalyst.

7. The method of claim 1, wherein said pattern of holes includes a disordered pattern of holes.

8. The method of claim 1, wherein said etching solution includes an acid selected from the group consisting of HF, HCl, HBr and HI.

9. The method of claim 1, wherein said etching solution includes an alcohol additive.

10. The method of claim 1, wherein said etch is performed in the absence of illuminating said semiconductor substrate.

11. A method for forming a thermoelectric element having a figure of merit (ZT) that is at least 0.25 at 25°

C., comprising;

(a) providing a semiconductor substrate in a reaction space comprising an etching solution;

(b) inducing flow of electrical current to said semiconductor substrate at a current density of at least 0.1 mA/cm²; and

(c) using said etching solution to etch said semiconductor substrate under said current density of at least 0.1 mA/cm² to form a disordered pattern of holes in said semiconductor substrate, thereby forming said thermoelectric element having said ZT that is at least about 0.25 at 25°

C., wherein said etching is performed (i) in the absence of a metal catalyst and (ii) at an electrical potential of at least 1 volt (V) across said semiconductor substrate and said etching solution, and

wherein said etching has an etch rate of at least 1 nanometer (nm) per second at 25°

C.

12. The method of claim 11, wherein said current density is at least 10 mA/cm².

13. The method of claim 12, wherein said current density is less than or equal to 50 mA/cm².

14. The method of claim 11, wherein said semiconductor substrate is etched under an alternating current at said current density.

15. The method of claim 11, wherein said etching solution includes an acid selected from the group consisting of HF, HCl, HBr and HI.

16. The method of claim 11, further comprising, prior to (c), heating said etching solution to a temperature that is greater than 25°

C.