Implementing dynamic phase error correction method and circuit for phase locked loop (PLL)
First Claim
1. A method for implementing dynamic phase error correction for a phase locked loop (PLL) comprising:
- providing a phase error correction circuit including an adjustable delay line placed in one of a reference clock path or a feedback clock path;
said phase error correction circuit,detecting a propagation delay of a reference clock path from input pin to a phase frequency detector in the PLL;
detecting a propagation delay of a feedback clock path from input pin to a phase frequency detector in the PLL;
comparing the detected propagation delays and generating a control signal proportional to a mismatch;
applying the generated control signal to the adjustable delay line, and continually adjusting a delay of the adjustable delay line until the reference and feedback paths are balanced.
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Abstract
A method and a circuit for implementing dynamic phase error correction for phase locked loop (PLL) circuits, and a design structure on which the subject circuit resides are provided. The circuit implements dynamic phase error correction and includes an adjustable delay line that is placed in either the reference or feedback clock path. The phase error correction circuit detects the propagation delay of the reference clock path from input pin to the phase frequency detector in the PLL. It also detects the propagation delay of the feedback clock path from input pin to the phase frequency detector in the PLL. The detected propagation delays are compared and a control signal is generated that is proportional to the mismatch. The control signal is applied to the adjustable delay line. The delay of the delay line is continually adjusted until the reference and feedback clock paths are balanced.
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Citations
15 Claims
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1. A method for implementing dynamic phase error correction for a phase locked loop (PLL) comprising:
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providing a phase error correction circuit including an adjustable delay line placed in one of a reference clock path or a feedback clock path; said phase error correction circuit, detecting a propagation delay of a reference clock path from input pin to a phase frequency detector in the PLL; detecting a propagation delay of a feedback clock path from input pin to a phase frequency detector in the PLL; comparing the detected propagation delays and generating a control signal proportional to a mismatch; applying the generated control signal to the adjustable delay line, and continually adjusting a delay of the adjustable delay line until the reference and feedback paths are balanced. - View Dependent Claims (2, 3, 4)
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5. A circuit for implementing dynamic phase error correction for a phase locked loop (PLL) comprising:
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a phase error correction circuit including an adjustable delay line placed in one of a reference clock path or a feedback clock path; said phase error correction circuit including a first phase detector detecting a propagation delay of a reference clock path from input pin to a phase frequency detector in the PLL; a second phase detector detecting a propagation delay of a feedback clock path from input pin to a phase frequency detector in the PLL; a charge pump comparing the detected propagation delays and generating a control signal proportional to a mismatch; said charge pump coupling the generated control signal to said adjustable delay line, and continually adjusting a delay of the adjustable delay line until the reference and feedback paths are balanced. - View Dependent Claims (6, 7, 8)
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9. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
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a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing dynamic phase error correction for a phase locked loop (PLL), said circuit comprising; a phase error correction circuit including an adjustable delay line placed in one of a reference clock path or a feedback clock path; said phase error correction circuit including a first phase detector detecting a propagation delay of a reference clock path from input pin to a phase frequency detector in the PLL; a second phase detector detecting a propagation delay of a feedback clock path from input pin to a phase frequency detector in the PLL; a charge pump comparing the detected propagation delays and generating a control signal proportional to a mismatch; said charge pump coupling the generated control signal to said adjustable delay line, and continually adjusting a delay of the adjustable delay line until the reference and feedback paths are balanced, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification