Implementing dynamic phase error correction method and circuit for phase locked loop (PLL)

• US 9,264,052 B1
• Filed: 01/20/2015
• Issued: 02/16/2016
• Est. Priority Date: 01/20/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kesselring, Grant P., Strom, James D., Steffen, Christopher W.
• Primary Examiner(s): Houston, Adam
• Application Number:
  US14/600,396
• Time in Patent Office: 392 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 1/1
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A method and a circuit for implementing dynamic phase error correction for phase locked loop (PLL) circuits, and a design structure on which the subject circuit resides are provided. The circuit implements dynamic phase error correction and includes an adjustable delay line that is placed in either the reference or feedback clock path. The phase error correction circuit detects the propagation delay of the reference clock path from input pin to the phase frequency detector in the PLL. It also detects the propagation delay of the feedback clock path from input pin to the phase frequency detector in the PLL. The detected propagation delays are compared and a control signal is generated that is proportional to the mismatch. The control signal is applied to the adjustable delay line. The delay of the delay line is continually adjusted until the reference and feedback clock paths are balanced.

Claims

1. A method for implementing dynamic phase error correction for a phase locked loop (PLL) comprising:

providing a phase error correction circuit including an adjustable delay line placed in one of a reference clock path or a feedback clock path;

said phase error correction circuit,

detecting a propagation delay of a reference clock path from input pin to a phase frequency detector in the PLL;

detecting a propagation delay of a feedback clock path from input pin to a phase frequency detector in the PLL;

comparing the detected propagation delays and generating a control signal proportional to a mismatch;

applying the generated control signal to the adjustable delay line, and continually adjusting a delay of the adjustable delay line until the reference and feedback paths are balanced.

2. The method as recited in claim 1 wherein providing a phase error correction circuit including an adjustable delay line placed in one of a reference path or a feedback path includes providing a voltage controlled delay line.

3. The method as recited in claim 2 wherein comparing the detected propagation delays and generating a control signal proportional to a mismatch includes providing a charge pump receiving the detected propagation delays and said charge pump generating a control voltage signal responsive to the received detected propagation delays.

4. The method as recited in claim 3 wherein said charge pump couples the generated control voltage signal to the voltage controlled delay line.

5. A circuit for implementing dynamic phase error correction for a phase locked loop (PLL) comprising:

a phase error correction circuit including an adjustable delay line placed in one of a reference clock path or a feedback clock path;

said phase error correction circuit including

a first phase detector detecting a propagation delay of a reference clock path from input pin to a phase frequency detector in the PLL;

a second phase detector detecting a propagation delay of a feedback clock path from input pin to a phase frequency detector in the PLL;

a charge pump comparing the detected propagation delays and generating a control signal proportional to a mismatch;

said charge pump coupling the generated control signal to said adjustable delay line, and continually adjusting a delay of the adjustable delay line until the reference and feedback paths are balanced.

6. The circuit as recited in claim 5 wherein said phase error correction circuit including said adjustable delay line placed in one of a reference clock path or a feedback clock path includes a voltage controlled delay line.

7. The circuit as recited in claim 6 wherein said charge pump comparing the detected propagation delays and generating a control signal proportional to a mismatch includes a charge pump receiving the detected propagation delays and said charge pump generating a control voltage signal responsive to the received detected propagation delays.

8. The circuit as recited in claim 7 wherein said charge pump couples the generated control voltage signal to the voltage controlled delay line.

9. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing dynamic phase error correction for a phase locked loop (PLL), said circuit comprising;

a phase error correction circuit including an adjustable delay line placed in one of a reference clock path or a feedback clock path;

said phase error correction circuit including

a first phase detector detecting a propagation delay of a reference clock path from input pin to a phase frequency detector in the PLL;

a second phase detector detecting a propagation delay of a feedback clock path from input pin to a phase frequency detector in the PLL;

a charge pump comparing the detected propagation delays and generating a control signal proportional to a mismatch;

said charge pump coupling the generated control signal to said adjustable delay line, and continually adjusting a delay of the adjustable delay line until the reference and feedback paths are balanced, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.

10. The design structure of claim 9, wherein the design structure comprises a netlist, which describes said PLL circuit.

11. The design structure of claim 9, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

12. The design structure of claim 9, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

13. The design structure of claim 9, wherein said phase error correction circuit including said adjustable delay line placed in one of a reference clock path or a feedback clock path includes a voltage controlled delay line.

14. The design structure of claim 9, wherein said charge pump generating a control voltage signal responsive to the received detected propagation delays.

15. The design structure of claim 14, wherein said charge pump couples the generated control voltage signal to the voltage controlled delay line.