Decision feedback equalizer for highly spectrally efficient communications

• US 9,264,179 B2
• Filed: 11/24/2014
• Issued: 02/16/2016
• Est. Priority Date: 06/20/2012
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: MagnaCom, Ltd. (Broadcom, Inc.)
• Inventors: Eliaz, Amir
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US14/551,393
• Publication Number:
  US 20150172078A1
• Time in Patent Office: 449 Days
• Field of Search: 375/229, 375/233, 375/348, 375/350
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/10 Means associated with receiver for limiting or suppressing noise or interference
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 17/15 Performance testing
• CPC Class Codes: H04B 17/29 Performance testing
• CPC Class Codes: H04B 2001/0416 having gain or transmission power control
• CPC Class Codes: H04L 1/0036 arrangements specific to the receiver
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0048 in conjunction with detection of multiuser or interfering signals, e.g. iteration between CDMA or MIMO detector and FEC decoder for spatial equalizer H04L25/03286
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 1/206 for modulated signals
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 23/02 adapted for orthogonal signalling
• CPC Class Codes: H04L 25/0236 using estimation of the other symbols
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03038 : with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03178 : Arrangements involving sequence estimation techniques
• CPC Class Codes: H04L 25/03197 : methods of calculation involving metrics
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/0328 : with interference cancellation circuitry adaptations for interference cancellation within a sequence estimator H04L25/03305; interference related aspects of direct sequence spread spectrum H04B1/7097; interference related aspects of frequency hopping spread spectrum H04B1/715; see also H04B1/10
• CPC Class Codes: H04L 25/03305 : Joint sequence estimation and interference removal joint detection of several desired signals H04L25/03331
• CPC Class Codes: H04L 25/03318 : Provision of soft decisions
• CPC Class Codes: H04L 25/03337 : Arrangements involving per-survivor processing
• CPC Class Codes: H04L 25/03343 : Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03834 : using pulse shaping
• CPC Class Codes: H04L 25/03885 : adaptive
• CPC Class Codes: H04L 25/03949 : equalizer selection or adaptation based on feedback multiple signaling inclusive of a precoding command for adapting the transmitter H04L1/0031; feedback for transmit diversity systems H04B7/0619; selection of codebook or precoding matrix for MIMO diversity systems H04B7/0456
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/00 : Modulated-carrier systems
• CPC Class Codes: H04L 27/01 : Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 27/02 : Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/04 : Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/2278 : using correlation techniques, e.g. for spread spectrum signals
• CPC Class Codes: H04L 27/36 : Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/366 : Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator
• CPC Class Codes: H04L 27/368 : adaptive predistortion
• CPC Class Codes: H04L 27/38 : Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/0058 : detection of error based on equalizer tap values
• CPC Class Codes: H04L 7/0087 : Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/02 : Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/042 : Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

One or more embodiments describe a decision feedback equalizer for highly spectrally efficient communications. A method may be performed in a decision feedback equalizer (DFE). The method may include initializing values of tap coefficients of the DFE based on values of tap coefficients of a partial response filter through which said transmitted symbols passed en route to said sequence estimation circuit. The method may include receiving estimates of transmitted symbols from a sequence estimation circuit, and receiving an error signal that is generated based on an estimated partial response signal output by the sequence estimation circuit. The method may include updating values of tap coefficients of the DFE based on the error signal and the estimates of transmitted symbols. The method may include generating one or more constraints that restrict the impact of the error signal on the updating of the values of the tap coefficients of the DFE.

Claims

1. A system comprising:

a filter circuit configured to output its tap coefficients to circuitry external to said filter circuit; and

a sequence estimation circuit operable to perform a sequence estimation process, wherein said tap coefficients of said filter circuit are an input to said sequence estimation process.

2. The system of claim 1, wherein said filter circuit accepts, as input, symbol decisions generated by said sequence estimation circuit.

3. The system of claim 1, wherein an output of said sequence estimation process is an estimate of phase error for a received signal input to said sequence estimation circuit.

4. The system of claim 3, wherein said filter circuit accepts, as input, said estimate of said phase error.

5. The system of claim 4, wherein said filter circuit is operable to adapt said tap coefficients based on said estimate of phase error.

6. The system of claim 1, wherein said filter circuit accepts, as input, an output of a feed forward equalizer of said receiver.

7. The system of claim 1, wherein said filter circuit accepts, as input, a partial response error signal.

8. The system of claim 7, wherein said partial response error signal is generated from an output of said sequence estimation circuit.

9. The system of claim 1, wherein said filter circuit is operable to generate soft decisions as to symbols output by said sequence estimation circuit.

10. The system of claim 1, wherein said filter circuit is a decision feedback equalizer.

11. A method comprising:

outputting, by a filter circuit of a receiver, tap coefficients to circuitry external to said filter circuit; and

performing, by a sequence estimation circuit of said receiver, a sequence estimation process, wherein said tap coefficients of said filter circuit are an input to said sequence estimation process.

12. The method of claim 11, comprising accepting by said filter circuit, as input, symbol decisions generated by said sequence estimation circuit.

13. The method of claim 11, comprising:

generating, by said sequence estimation circuit, an estimate of phase error for a received signal input to said sequence estimation circuit.

14. The method of claim 13, comprising accepting by said filter circuit, as input, said estimate of said phase error.

15. The method of claim 14, comprising adapting, by said filter circuit, said tap coefficients based on said estimate of phase error.

16. The method of claim 11, comprising accepting by filter circuit, as input, an output of a feed forward equalizer of said receiver.

17. The method of claim 11, comprising accepting by said filter circuit, as input, a partial response error signal.

18. The method of claim 17, wherein said partial response error signal is generated from an output of said sequence estimation circuit.

19. The method of claim 11, comprising generating, by said filter circuit, soft decisions as to symbols output by said sequence estimation circuit.

20. The method of claim 11, wherein said filter circuit is a decision feedback equalizer.