Storage method and apparatus for random access memory using codeword storage

• US 9,268,683 B1
• Filed: 03/15/2013
• Issued: 02/23/2016
• Est. Priority Date: 05/14/2012
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Cronie, Harm, Shokrollahi, Amin
• Primary Examiner(s): Tu, Christine
• Application Number:
  US13/844,032
• Time in Patent Office: 1,075 Days
• Field of Search: 371/763, 371/773, 371/778, 371/758, 365/189.011, 365/189.04, 365/189.14, 365/189.15, 365/189.16, 365/201
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1505 Golay Codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that are stored and defined by a Hadamard matrix. The storage format word is stored as charge levels in an addressable memory location. For retrieving stored data, charge levels are read from the storage cells and interpreted to a valid storage format word. Hadamard code maximal likelihood decoding can be used to derive a read data word corresponding to a previously written write data word. The write data word is then output as the result of a read of the selected addressable location, or a portion thereof. The mapping can be two or more Hadamard matrix mappings concatenated for each of a plurality of storage format words.

Claims

1. A method comprising:

accepting a write data word, wherein the write data word is representable as a vector having a plurality of components;

mapping the write data word to a storage format word of a plurality of storage format words, wherein the storage format word is representable as a vector having a plurality of components wherein each storage format word represents a subtraction between (i) a weighted all-one Walsh function and (ii) a respective unique summation of at least one Walsh function of a plurality of Walsh functions, the all-one Walsh function corresponding to an all-one row of a Hadamard matrix and each Walsh function of the plurality of Walsh functions corresponding to a respective row of the Hadamard matrix, and wherein the components of the storage format-word vector have magnitudes greater than or equal to zero;

determining a selected subset of the plurality of storage cells according to an address input; and

storing the components of the storage format word as charge levels on the selected subset of the plurality of storage cells.

2. The method of claim 1, wherein each storage cell in the selected subset is configured to store a bit value, the bit value having one of two possible logical values, and storing a charge level comprises storing one of two possible charge levels.

3. The method of claim 1, wherein each component of the vector representing a write data word is a bit, the bit having one of two possible logical values and accepting each component comprises reading one of two possible logical values.

4. The method of claim 1, further comprising:

determining a read target address;

determining a selected read target subset of the plurality of storage cells according to the read target address;

measuring the charge levels on the multiple storage cells of the selected read target subset;

interpreting the measured charge levels as a maximal likelihood decoding of a presumed write data word; and

producing a read data word from the interpreted charge levels.

5. The method of claim 4, wherein mapping further comprises a distribution operation that spreads the write data word across multiple Hadamard encodings, each Hadamard encoding comprising a respective storage format word, and producing further comprises combining the result of the multiple Hadamard decodings to produce the read data word.

6. The method of claim 4, wherein the maximal likelihood decoding comprises decoding a Hadamard code, wherein decoding the Hadamard code comprises using a Fast Walsh Transform.

7. The method of claim 1, wherein the subset of the plurality of storage cells is selected by an array address comprising a row selection element and a column selection element, individual cells within the selected subset having at least the row selection element in common.

8. The method of claim 1, where at least one of the write data word and the storage format word incorporates additional error detection or error correction bits.

9. The method of claim 1, wherein the write data word comprises B elements, and the storage format word comprises 2^B+1−

1 components, wherein B is an integer greater than or equal to 1.

10. The method of claim 1, wherein the summation of at least one Walsh function comprises n Walsh functions, and a weight of n is applied to the all-one Walsh function, wherein n is an integer greater than or equal to 1.

11. A system for storing digital data, comprising:

a dynamic memory structure of multiple storage cells configured to retain a volatile electrical charge;

a signal encoder configured to create a Hadamard coded storage format word from a data input, wherein the storage format word is representable as a vector having a plurality of components wherein each Hadamard coded storage format word represents a summation of (i) a weighted all-one Walsh function and (ii) a respective unique summation of at least one Walsh function of a plurality of Walsh functions, the all-one Walsh function corresponding to an all-one row of a Hadamard matrix and each Walsh function of the plurality of Walsh functions corresponding to a respective row of the Hadamard matrix, and wherein the components of the storage format-word vector have magnitudes greater than or equal to zero;

a dynamic memory write circuit configured to store the Hadamard coded storage format word as charge levels on a selected subset of the multiple storage cells;

a dynamic memory read circuit configured to measure the charge levels on a selected subset of the multiple storage cells;

a signal decoder configured to interpret the measured charge levels as a maximal likelihood decoding of the Hadamard coded storage format word; and

a data output derived from the maximal likelihood decoding.

12. The system of claim 11, further comprising a dynamic memory refresh circuit configured to:

obtain the maximal likelihood decoding of the Hadamard coded storage format word;

create a new Hadamard coded storage format word from the maximum likelihood decoding; and

store the new Hadamard coded storage format word as charge levels on the same selected subset of the multiple storage cells.

13. The system of claim 11, wherein the data input comprises B elements, and the Hadamard coded storage format word comprises 2^B+1−

1 components, wherein B is an integer greater than or equal to 1.

14. The system of claim 11, wherein each storage cell is configured to store a bit value, the bit value having one of two possible logical values, and the dynamic memory write circuit is configured to store each charge level as one of two possible charge levels.

15. The system of claim 11, wherein each component of the vector representing a write data word is a bit, the bit having one of two possible logical values and the signal encoder is configured to detect each component by reading one of two possible logical values.

16. The system of claim 11, wherein each component of the Hadamard coded storage format word comprises values selected from a set of three possible values.

17. The system of claim 16, wherein each value in the set of three possible value has a magnitude greater than or equal to 0, and less than or equal to 1.

18. The system of claim 16, wherein the dynamic memory write circuit is configured to store each charge level as one of three possible charge levels.

19. The system of claim 11, wherein the summation of at least one Walsh function comprises n Walsh functions, and a weight of n is applied to the all-one Walsh function, wherein n is an integer greater than or equal to 1.

20. The system of claim 11, where at least one of the data input and the Hadamard coded storage format word incorporates additional error detection or error correction bits.