Memory signal buffers and modules supporting variable access granularity

• US 9,268,719 B2
• Filed: 08/03/2012
• Issued: 02/23/2016
• Est. Priority Date: 08/05/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Shyu, Jing-Yih
• Application Number:
  US13/566,417
• Publication Number:
  US 20130036273A1
• Time in Patent Office: 1,299 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.

Claims

1. A memory module comprising:

a signal buffer having a module data interface to communicate module data, a module command interface to receive module commands, a first memory data interface, a second memory data interface, a first memory command interface, and a second memory command interface separate from the first memory command interface;

a first memory device group, including at least one memory device, the first memory device group receiving first-memory commands from the first memory command interface and communicating first-memory data with the first memory data interface; and

a second memory device group, separate from the first memory device group and comprising at least one memory device, the second memory device group receiving second-memory commands from the second memory command interface and communicating second-memory data with the second memory data interface;

the signal buffer having steering logic to derive the first-memory commands and the second-memory commands from the module commands, and to communicate the module data associated with each module command between the module data interface and one of the first or second memory device groups as the first or second memory data, respectively;

wherein the steering logic conveys the module data associated with each module command between the module data interface and one of the first and second memory data interfaces in a first mode and conveys the module data associated with each module command between the module data interface and both the first and second memory data interfaces in a second mode.

2. The memory module of claim 1, wherein the signal buffer includes a mode register to store a value indicative of the first mode or the second mode.

3. The memory module of claim 1, wherein the signal buffer, responsive to one of the module commands, issues multiple ones of the first-memory commands to the first memory device group.

4. The memory module of claim 3, wherein the multiple ones of the first-memory commands each specify the same row address.

5. The memory module of claim 3, wherein the signal buffer receives the first-memory data in multiple, successive column accesses responsive to the multiple ones of the first-memory commands and combines the column accesses to concurrently convey the first-memory data of the successive column accesses to the module data interface.

6. The memory module of claim 5, wherein the signal buffer conveys the data from the successive column accesses on separate subsets of pins in the module data interface.

7. The memory module of claim 5, wherein the signal buffer conveys the data from the successive column accesses, at different times, on a subset of pins in the module data interface.

8. The memory module of claim 1, wherein the signal buffer concurrently conveys the first and second memory data to the module data interface in a first mode and successively conveys the first and second memory data from the respective first and second memory device groups to the module data interface in a second mode.

9. The memory module of claim 8, wherein the signal buffer successively conveys the first and second memory data from the first and second memory device groups over a subset of all data pins of the module data interface.

10. The memory module of claim 1, wherein module data interface includes 2N data pins, the first memory command interface includes N data pins, and the second memory command interface includes N data pins.

11. The memory module of claim 10, wherein the signal buffer, responsive to the module commands, conveys an N-wide burst of data from the first memory device group and an N-wide burst of data from the second memory device group.

12. The memory module of claim 11, wherein the signal buffer, responsive to the module commands, combines the N-wide bursts of data from the first and second memory device groups into a 2N-wide burst of data on the module data interface.

13. The memory module of claim 12, wherein the signal buffer interleaves the N-wide bursts from the first and second memory device groups to produce the 2N-wide burst.

14. The memory module of claim 12, wherein the N-wide bursts of data are of a length M, and the signal buffer reorders the N-wide bursts to a length less than M.

15. The memory module of claim 1, wherein the first-memory data from the first memory command interface and the second-memory data from the second memory command interface each include at least one of a data-mask signal, a data-bus-inversion signal, and an error-detection-code signal.

16. The memory module of claim 1, wherein the module commands include a column-access-strobe command, and wherein the signal buffer translates the column-access-strobe command into two secondary column-access-strobe commands.

17. The memory module of claim 16, wherein the signal buffer successively conveys the two secondary column-access-strobe commands to one of the first and second memory device groups.

18. The memory module of claim 1, wherein the first memory device group comprises a first rank of interconnected memory devices, and the second memory device group comprises a second rank of interconnected memory devices.

19. A memory module comprising:

a signal buffer having a module data interface to communicate module data, a module command interface to receive module commands, a first memory data interface, a second memory data interface, a first memory command interface, and a second memory command interface separate from the first memory command interface;

a first memory device group, including at least one memory device, the first memory device group receiving first-memory commands from the first memory command interface and communicating first-memory data with the first memory data interface; and

a second memory device group, separate from the first memory device group and comprising at least one memory device, the second memory device group receiving second-memory commands from the second memory command interface and communicating second-memory data with the second memory data interface;

the signal buffer having steering logic to derive the first-memory commands and the second-memory commands from the module commands, and to communicate the module data associated with each module command between the module data interface and one of the first or second memory device groups as the first or second memory data, respectively;

wherein the module commands include at least one of a row-address signal, and a chip-select signal, and wherein the signal buffer selects between the first and second memory device groups based on the at least one of the row-address signal, and the chip-select signal.