Load balancing scheme in multiple channel DRAM systems

• US 9,268,720 B2
• Filed: 08/31/2010
• Issued: 02/23/2016
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Feng, Gu, Shiqun, Kim, Jonghae, Nowak, Matthew Michael
• Primary Examiner(s): Sadler, Nathan
• Application Number:
  US12/872,282
• Publication Number:
  US 20120054423A1
• Time in Patent Office: 2,002 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 2213/0064 Latency reduction in handling transfers

Abstract

A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

Claims

1. A method for load balancing in a multiple channel Dynamic Random Access Memory (DRAM) system, the method comprising:

interleaving memory data across two or more memory channels;

controlling access to the two or more memory channels with memory controllers;

coupling bus masters to the memory controllers via an interconnect system;

transmitting memory requests from the bus masters to the memory controllers;

detecting congestion in a first memory channel in response to a memory request to a first memory controller by tracking a number of memory requests which are denied by the first memory controller, and determining that congestion exists in the first memory channel if a predetermined threshold number of denials of the memory requests by the first memory controller is reached;

generating a congestion signal for the first memory channel;

transmitting the congestion signal to the bus masters; and

rerouting the memory request to a second memory controller in response to the congestion signal, wherein the rerouting comprises remapping a memory address association for the memory request from a first physical address in the first memory channel to a second physical address in a second memory channel coupled to the second memory controller, wherein a second congestion signal for the second memory channel is not asserted.

2. The method of claim 1, wherein the congestion signal comprises a single binary bit to represent congestion.

3. The method of claim 1, wherein the congestion signal comprises two or more binary bits to represent a range of congestion levels.

4. The method of claim 1, further comprising withdrawing the memory request to the first memory controller in response to the congestion signal.

5. The method of claim 1, wherein the DRAM system is integrated in at least one semiconductor die.

6. The method of claim 1, wherein the DRAM system is integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

7. A Dynamic Random Access Memory (DRAM) system comprising:

memory data interleaved across two or more memory channels;

memory controllers for controlling access to the two or more memory channels;

bus masters coupled to the memory controllers via an interconnect system, wherein the bus masters are configured to transmit memory requests to the memory controllers;

logic configured to generate a congestion signal for a first memory channel coupled to a first memory controller in response to a memory request, if a predetermined threshold number of denials of memory requests by the first memory controller is reached; and

logic configured to alter an address mapping for the memory request in a memory management unit (MMU) from an association to a first physical address in the first memory channel to a second physical address in a second memory channel wherein a second congestion signal for the second memory channel is not asserted, in order to reroute the memory request to a second memory controller coupled to the second memory channel, in response to the congestion signal.

8. The DRAM system of claim 7, wherein the congestion signal comprises a single binary bit to indicate congestion.

9. The DRAM system of claim 7, wherein the congestion signal comprises two or more binary bits to indicate a range of congestion levels.

10. The DRAM system of claim 7 further comprising logic configured to transmit the congestion signal to the bus masters.

11. The DRAM system of claim 10, further comprising logic to withdraw the memory request to the first memory controller, in response to the congestion signal.

12. The DRAM system of claim 7 integrated in at least one semiconductor die.

13. The DRAM system of claim 7 integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

14. A Dynamic Random Access Memory (DRAM) system comprising:

channel means for accessing memory data, wherein memory data is interleaved across two or more channel means;

controller means for controlling access to the channel means;

means for coupling bus masters to the controller means via an interconnect means;

means for transmitting memory requests from the bus masters to the controller means;

means for generating a congestion indication for a first channel means coupled to a first controller means, in response to a memory request, comprising means for tracking a number of memory requests which are denied by the first controller means and means for determining that congestion exists if a predetermined threshold number of denials of the memory requests by the first controller means is reached; and

means for rerouting the memory request to a second memory controller means in response to the congestion indication, comprising means for remapping a memory address association for the memory request from a first physical address in the first channel means to a second physical address in the second channel means coupled to the second controller means, wherein a second congestion signal for the second channel means is not asserted.

15. The DRAM system of claim 14, wherein the congestion indication comprises binary signal means for indicating congestion.

16. The DRAM system of claim 14, wherein the congestion indication comprises binary signal means to indicate a range of congestion levels.

17. The DRAM system of claim 14, further comprising means for transmitting the congestion indication to the bus masters.

18. The DRAM system of claim 17, further comprising means for withdrawing the memory request to the first controller means, in response to the congestion indication.

19. The DRAM system of claim 14 integrated in at least one semiconductor die.

20. The DRAM system of claim 14 integrated into a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.

21. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for load balancing in a multiple channel Dynamic Random Access Memory (DRAM) system, the non-transitory computer-readable storage medium comprising:

code for interleaving memory data across two or more memory channels;

code for controlling access to the two or more memory channels with memory controllers;

code for coupling bus masters to the memory controllers via an interconnect system;

code for transmitting memory requests from the bus masters to the memory controllers;

code for detecting congestion in a first memory channel in response to a memory request to a first memory controller by tracking a number of memory requests which are denied by the first memory controller, and determining that congestion exists in the first memory controller if a predetermined threshold number of denials of the memory requests by the first memory controller is reached;

code for generating a congestion signal for the first memory channel;

code for transmitting the congestion signal to the bus masters; and

code for rerouting the memory request to a second memory controller in response to the congestion signal, comprising code for remapping a memory address association for the memory request from a first physical address in the first memory channel to a second physical address in a second memory channel coupled to the second memory controller, wherein a second congestion signal for the second memory channel is not asserted.