Systems and methods for efficient handling of data traffic and processing within a processing device
First Claim
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1. A processing device, comprising:
- a housing;
a chip housed in the housing;
a first processing agent housed in the housing and connected to the chip; and
a network interface operable to connect the processing device to an external network that is external to the housing, whereinthe chip comprises;
an interconnect;
a second processing agent communicatively connected to the interconnect, the second processing agent comprising a plurality of general purpose processor cores and a cache memory;
a network adapter communicatively connected to the interconnect and to the network interface, the network adapter being operable to receive and classify protocol packets received from the network interface; and
an accelerating agent communicatively connected to the interconnect, the accelerating agent being adapted to perform acceleration operations, whereinthe network adapter is configured red such that in response to receiving a packet comprising a header and a payload, the network adapter uses the interconnect to store the payload in the cache memory of the second processing agent.
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Abstract
The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power.
54 Citations
19 Claims
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1. A processing device, comprising:
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a housing; a chip housed in the housing; a first processing agent housed in the housing and connected to the chip; and a network interface operable to connect the processing device to an external network that is external to the housing, wherein the chip comprises; an interconnect; a second processing agent communicatively connected to the interconnect, the second processing agent comprising a plurality of general purpose processor cores and a cache memory; a network adapter communicatively connected to the interconnect and to the network interface, the network adapter being operable to receive and classify protocol packets received from the network interface; and an accelerating agent communicatively connected to the interconnect, the accelerating agent being adapted to perform acceleration operations, wherein the network adapter is configured red such that in response to receiving a packet comprising a header and a payload, the network adapter uses the interconnect to store the payload in the cache memory of the second processing agent. - View Dependent Claims (2, 3, 4, 5)
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6. A chip for use in a network server comprising a first processing agent and a network interface, said chip comprising:
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an interconnect; a second processing agent communicatively connected to the interconnect, the second processing agent comprising a plurality of general purpose processor cores and a cache memory; a network adapter communicatively connected to the interconnect and to the network interface, the network adapter being operable to receive and classify protocol packets received from the network interface; and an accelerating agent communicatively connected to the interconnect, the accelerating agent being adapted to perform acceleration operations, wherein the network adapter is configured such that, in response to receiving a packet comprising a header and a payload, the network adapter uses the interconnect to store the payload in the cache memory of the second processing agent. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A chip for use in a processing device, said chip comprising:
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an interconnect; a packet processor communicatively connected to the interconnect and communicatively connected to a network interface, the packet processor being operable to receive packet via the network interface; and a processing agent communicatively connected to the interconnect, the processing agent comprising a plurality of processor cores and cache memory, wherein the packet processor is configured to; parse a received packet and perform one or more actions based on information contained in the received packet, wherein said actions include providing at least a portion of the received packet to the cache memory of the processing agent via the interconnect. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification