Integrated circuit device methods and models with predicted device metric variations

• US 9,268,885 B1
• Filed: 02/28/2013
• Issued: 02/23/2016
• Est. Priority Date: 02/28/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Wang, Jing
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US13/780,006
• Time in Patent Office: 1,090 Days
• Field of Search: 716/106, 716/107, 716/111, 716/112, 716/113, 716/136
• US Class Current: 1/1
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method can include selecting integrated circuit (IC) device fabrication process source variations; generating relationships between each process source variance and a device metric variance; and calculating at least one IC device metric value from the process source variations and corresponding relationships between each process source variance and a device metric variance.

Claims

1. A method, comprising:

assuming variation among process targets for a plurality of integrated circuit (IC) fabrication process sources of variation;

deriving relationships between each process source variance of the IC fabrication process and a device metric variance by operation of a computer program executed by a computer, the device metric variance being a variance in an IC performance characteristic;

generating a predicted device metric variation by at least multiplying each process source variation by the corresponding relationships between its process source variance and the device metric variance; and

designing at least a portion of an integrated circuit with the predicted device metric variation;

wherein.

generating the predicted device metric variation includes

calculating a root sum square of process source variations and the relationships between the corresponding process source variance and the device metric variance;

designing the at least a portion of the integrated circuit includes selecting process source variations having a greatest effect on the predicted device metric variation and creating a transistor performance model from at least the device metric; and

fabricating the at least a portion of the integrated circuit with the predicted device metric variation.

2. The method of claim 1, wherein:

the relationships are generated from a semiconductor design automation tool executed by the computer.

3. The method of claim 2, wherein:

the relationships are generated from a technology computer aided design (TCAD) automation tool.

4. The method of claim 1, wherein:

the assumed variation values correspond to an IC fabrication process still under development.

5. A method, comprising:

assuming variation among process targets for a plurality of integrated circuit (IC) fabrication process sources of variation;

deriving relationships between each process source variance of the I C fabrication process and a device metric variance by operation of a computer program executed by a computer, the device metric variance being a variance in an I C performance characteristic;

generating a predicted device metric variation by at least multiplying each process source variation by the corresponding relationships between its process source variance and the device metric variance; and

designing at least a portion of an integrated circuit with the predicted device metric variation;

wherein

generating the predicted device metric variation includes

generating a device metric distribution from process source variation distributions and the relationships between the corresponding process source variance and the device metric variance;

designing the at least a portion of the integrated circuit includes any selected from the group consisting of;

deriving correlations between device metrics and deriving correlations between device types; and

fabricating the at least a portion of the integrated circuit with the predicted device metric variation.

6. The method of claim 5, wherein:

the relationships are generated from a semiconductor design automation tool executed by the computer.

7. The method of claim 6, wherein:

the relationships are generated from a technology computer aided design (TCAD) automation tool.

8. The method of claim 5, wherein:

the assumed variation values correspond to an IC fabrication process still under development.

9. A method, comprising:

assuming variation among process targets for a plurality of integrated circuit (IC) fabrication process sources of variation;

deriving relationships between each process source variance of the IC fabrication process and a device metric variance by operation of a computer program executed by a computer, the device metric variance being a variance in an IC performance characteristic;

generating a predicted device metric variation by at least multiplying each process source variation by the corresponding relationships between its process source variance and the device metric variance; and

designing at least a portion of an integrated circuit with the predicted device metric variation;

wherein

generating the predicted device metric variation includes generating a corner device metric corresponding to corner process

source values, the corner process source values corresponding to an extreme end of a range of possible process source values;

designing the at least a portion of the integrated circuit includes designing a transistor model with at least the corner device metric; and

fabricating the at least a portion of the integrated circuit with the predicted device metric variation.

10. The method of claim 9, wherein:

the relationships are generated from a semiconductor design automation tool executed by the computer.

11. The method of claim 10, wherein:

the relationships are generated from a technology computer aided design (TCAD) automation tool.

12. The method of claim 9, wherein:

the assumed variation values correspond to an IC fabrication process still under development.