Encryption-and decryption-enabled interfaces
First Claim
Patent Images
1. Decryption apparatus, comprising:
- an input memory, which is coupled to receive encrypted data that have been transmitted to the apparatus over a network and written to the input memory;
an output transducer, for presenting decrypted data to a user;
a decryption processor, which is coupled to read and decrypt the encrypted data from the input memory but is incapable of writing to the input memory, due to lack of a hardware connection between a write output of the decryption processor and the input memory, and which decryption processor is coupled to convey the decrypted data to the output transducer for presentation to the user; and
an output memory, which is coupled to receive the decrypted data from the decryption processor and to output the decrypted data to the output transducer,wherein the input memory is coupled to receive the encrypted data from a central processing unit (CPU) of a computer, and wherein the output memory is inaccessible to the CPU, due to lack of a hardware connection between the output memory and the CPU.
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Abstract
Decryption apparatus includes an input memory (48), which is coupled to receive encrypted data, and an output transducer (28), for presenting decrypted data to a user. A decryption processor (50) is coupled to read and decrypt the encrypted data from the input memory but is incapable of writing to the input memory, and is coupled to convey the decrypted data to the output transducer for presentation to the user.
190 Citations
19 Claims
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1. Decryption apparatus, comprising:
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an input memory, which is coupled to receive encrypted data that have been transmitted to the apparatus over a network and written to the input memory; an output transducer, for presenting decrypted data to a user; a decryption processor, which is coupled to read and decrypt the encrypted data from the input memory but is incapable of writing to the input memory, due to lack of a hardware connection between a write output of the decryption processor and the input memory, and which decryption processor is coupled to convey the decrypted data to the output transducer for presentation to the user; and an output memory, which is coupled to receive the decrypted data from the decryption processor and to output the decrypted data to the output transducer, wherein the input memory is coupled to receive the encrypted data from a central processing unit (CPU) of a computer, and wherein the output memory is inaccessible to the CPU, due to lack of a hardware connection between the output memory and the CPU. - View Dependent Claims (2, 3, 4, 5, 6, 7, 17, 19)
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8. A method for decryption, comprising:
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receiving encrypted data that have been transmitted over a network from a central processing unit (CPU) of a computer and writing the received encrypted data to an input memory; reading and decrypting the encrypted data from the input memory using a decryption processor, which is incapable of writing to the input memory, due to lack of a hardware connection between a write output of the decryption processor and the input memory; and conveying the decrypted data from the decryption processor to an output transducer for presentation to a user, through an output memory, which is coupled to receive the decrypted data from the decryption processor and to output the decrypted data to the output transducer, wherein the output memory is inaccessible to the CPU, due to lack of a hardware connection between the output memory and the CPU. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 18)
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Specification