Devices and methods for reducing power consumption and size of gate drivers

• US 9,269,319 B2
• Filed: 09/30/2014
• Issued: 02/23/2016
• Est. Priority Date: 10/17/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Luh, Louis, Huang, Chun-Yao
• Primary Examiner(s): VU, JIMMY T
• Application Number:
  US14/502,856
• Publication Number:
  US 20150108916A1
• Time in Patent Office: 511 Days
• Field of Search: 3151691-1693, 315223-225, 315/291, 315/307, 345 87-100, 345/304, 345/211
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

One gate driver includes an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of a display. An input node of the gate driver is configured to receive an input signal. The gate driver includes a first field-effect transistor (FET) having a gate, a drain, and a source. The drain may be coupled to the input node and the source may be coupled to the output node. The gate driver also includes a second FET having a gate, a drain, and a source. The drain may be coupled to the input node. The gate driver includes a capacitor having a first end coupled to the gates of the FETs and a second end coupled to the source of the second FET. Using the gate driver power consumption of the display may be reduced.

Claims

1. A display for an electronic device, comprising:

a gate driver comprising;

an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of the display;

an input node configured to receive an input signal;

a first field-effect transistor (FET) having a first gate, a first drain, and a first source, wherein the first drain is coupled to the input node and the first source is coupled to the output node;

a second FET having a second gate, a second drain, and a second source, wherein the second drain is coupled to the input node; and

a capacitor having a first end and a second end, wherein the first end of the capacitor is coupled to the first gate and the second gate, and the second end of the capacitor is coupled to the second source.

2. The display of claim 1, wherein the input node is configured to receive a clock signal as the input signal.

3. The display of claim 1, wherein the first FET is a first metal-oxide-semiconductor FET (MOSFET) and the second FET is a second MOSFET.

4. The display of claim 3, wherein the first MOSFET is a first n-channel MOSFET (NMOS) and the second MOSFET is a second NMOS.

5. The display of claim 1, wherein the gate driver comprises a set node configured to provide power to the first end of the capacitor to charge the capacitor.

6. The display of claim 1, wherein the gate driver comprises circuitry coupled to the first end of the capacitor and configured to drive the first end of the capacitor toward a low voltage.

7. The display of claim 1, wherein the gate driver comprises circuitry coupled to the second end of the capacitor and configured drive the second end of the capacitor toward a low voltage.

8. The display of claim 7, wherein the circuitry comprises a third FET.

9. A gate driver for an electronic display, comprising:

an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of the display;

an input node configured to receive an input signal;

a field-effect transistor (FET) having a gate, a drain, and a source, wherein the drain is coupled to the input node and the source is coupled to the output node;

a capacitor having a first end and a second end, wherein the first end of the capacitor is coupled to the gate of the FET; and

a plurality of latching circuits coupled to the first end of the capacitor and configured to alternatively drive the first end of the capacitor toward a low voltage.

10. The gate driver of claim 9, wherein each latching circuit of the plurality of latching circuits comprises a latching FET having a second gate, a second drain, and a second source, and an inverter having an inverter input, an inverter output, and an enable input node.

11. The gate driver of claim 10, wherein the inverter input is coupled to the first end of the capacitor, the inverter output is coupled to the second gate, the second drain is coupled to the first end of the capacitor, the second source is coupled to a common reference node, and the enable input is configured to selectively enable the inverter to invert a signal provided to the inverter input and to provide the inverted signal to the inverter output.

12. The gate driver of claim 9, wherein each latching circuit of the plurality of latching circuits comprises a latching FET having a second gate, a second drain, and a second source, a latching capacitor, and an enable input node.

13. The gate driver of claim 12, wherein the latching capacitor is coupled to the enable input node and to the second gate, the second drain is coupled to the first end of the capacitor, and the second source is coupled to a common reference node.

14. An electronic device comprising:

a gate driver comprising;

an output node configured to be coupled to a gate line and to provide power to the gate line;

an input node configured to receive an input signal;

a first field-effect transistor (FET) having a first gate, a first drain, and a first source, wherein the first drain is coupled to the input node and the first source is coupled to the output node;

a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to the first gate; and

a latching circuit comprising;

a second FET having a second gate, a second drain, and a second source;

a third FET having a third gate, a third drain, and a third source;

a second capacitor having a first end and a second end; and

a reset node configured to receive a reset signal for driving the first end of the first capacitor toward a low voltage, wherein the reset node is coupled to the second gate and the second drain, the second source is coupled to the first end of the second capacitor and to the third gate, the third drain is coupled to the first end of the first capacitor, and the second end of the second capacitor is coupled to the third source.

15. The electronic device of claim 14, comprising an electronic display having the gate driver.

16. The electronic device of claim 14, wherein at least one of the first, second, and third FETs comprises a metal-oxide-semiconductor FET (MOSFET).

17. The electronic device of claim 14, comprising a fourth FET having a fourth gate, a fourth drain, and a fourth source, wherein the fourth drain is coupled to the input node, the fourth gate is coupled to the first end of the first capacitor, and the fourth source is coupled to the second end of the first capacitor.

18. A method comprising:

activating a first enable node of a gate driver to enable a first latching circuit of the gate driver;

deactivating a second enable node of the gate driver to disable a second latching circuit of the gate driver while activating the first enable node; and

activating a precharge node of the gate driver while the first latching circuit is enabled to store a first charge in a first capacitor of the first latching circuit.

19. The method of claim 18, comprising deactivating the precharge node after activating the precharge node and activating a first field-effect transistor (FET) using the first charge of the first capacitor to charge a second capacitor.

20. The method of claim 19, comprising activating a set node of the gate driver after deactivating the precharge node to discharge the first capacitor and to charge the second capacitor.

21. The method of claim 20, comprising deactivating the set node after activating the set node and applying a clock pulse to activate an output node of the gate driver.

22. An electronic display comprising:

a gate driver comprising;

a capacitor having a first end and a second end;

a first latching circuit coupled to the first end of the capacitor and configured to couple the first end of the capacitor to a common reference node while enabled and while charged;

a first enable node configured to receive a first signal to enable the first latching circuit;

a second latching circuit coupled to the first end of the capacitor and configured to couple the first end of the capacitor to the common reference node while enabled and while charged;

a second enable node configured to receive a second signal to enable the second latching circuit;

a precharge input node configured to receive a third signal to charge the first latching circuit, to charge the second latching circuit, or some combination thereof;

a set input node configured to receive a fourth signal to charge the capacitor;

an output node configured to be coupled to a gate line and to provide power to the gate line for driving thin-film transistor (TFT) gates of the electronic display; and

a clock input node configured to receive a fifth signal configured to charge the capacitor and to provide an output signal to the output node.

23. The electronic display of claim 22, wherein the gate driver comprises a reset input node configured to receive a sixth signal to charge the first latching circuit, to charge the second latching circuit, or some combination thereof.

24. The electronic display of claim 22, wherein the gate driver comprises a clear input node configured to receive a sixth signal to couple the first end of the capacitor to the common reference node, to couple the second end of the capacitor to the common reference node, and to couple the output node to the common reference node.

25. The electronic display of claim 22, wherein the set input node is configured to receive the fourth signal from a second output node of a second gate driver, and wherein the clock input node is the only input to the gate driver configured to receive a clock signal.