Isolation switching for backup memory

• US 9,269,437 B2
• Filed: 09/17/2014
• Issued: 02/23/2016
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Chen, Chi-She, Solomon, Jeffrey C., Milton, Scott H., Bhakta, Jayesh
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US14/489,332
• Publication Number:
  US 20150255156A1
• Time in Patent Office: 524 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

Claims

1. A memory module comprising:

a host interface operable to be coupled to a host computer, the host interface including a standard dual inline memory module (DIMM) interface configured to be in electrical communication with the host computer using double data rate synchronous dynamic random-access memory (DDR SDRAM) data signals and DDR SDRAM address and control (addr/cont) signals;

a circuit coupled to the host interface using a data bus and an addr/cont bus, the circuit configured to be in electrical communication with the host interface (i) using DDR SDRAM data signals by way of the data bus, and (ii) using DDR SDRAM addr/cont signals by way of the addr/cont bus;

a volatile memory subsystem coupled to the circuit using a first data bus and a first addr/cont bus, the volatile memory subsystem including one or more DDR SDRAM memory elements, the volatile memory subsystem configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the first data bus, and (ii) using DDR SDRAM addr/cont signals by way of the first addr/cont bus;

a controller coupled to the circuit using a second data bus and a second addr/cont bus, the controller configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the second data bus, and (ii) using DDR SDRAM addr/cont signals by way of the second addr/cont bus; and

a non-volatile memory subsystem coupled to the controller, the non-volatile memory subsystem including one or more flash memory elements, the controller operable to manage the non-volatile memory subsystem, wherein, in response to signals from the controller, the circuit is operable to transfer data (i) between the host computer and the volatile memory subsystem by way of the data bus and the first data bus, and (ii) between the non-volatile memory subsystem and the volatile memory subsystem by way of the first data bus and the second data bus.

2. The memory module of claim 1, further comprising:

a voltage monitor circuit coupled to the controller by way of a control signal line, the voltage monitor circuit operable to (i) monitor a supply voltage provided by the host computer to the memory module via the standard DIMM interface, (ii) generate a control signal in response to a change in the supply voltage, and (iii) transmit the control signal to the controller by way of the control signal line.

3. The memory module of claim 2, wherein, in response to the control signal, the controller is operable to control data transfer between the volatile memory subsystem and the non-volatile memory subsystem by way of the circuit, the first data bus and the second data bus.

4. The memory module of claim 3, wherein the circuit is operable to (i) receive a first set of DDR SDRAM addr/cont signals from the controller by way of the second addr/cont bus, (ii) transmit the first set of the DDR SDRAM addr/cont signals to the volatile memory subsystem by way of the first addr/cont bus, and (iii) transfer a first data signal from the volatile memory subsystem to the controller by way of the first data bus and the second data bus.

5. The memory module of claim 4, wherein a portion of the controller is dedicated to generate address and control signals for the non-volatile memory subsystem, and wherein the controller is operable to write the first data signal into the non-volatile memory subsystem using the generated address and control signals for the non-volatile memory subsystem.

6. The memory module of claim 1, wherein the circuit is operable to transfer data between the volatile memory subsystem and the host computer by way of the first data bus, the data bus, and the standard DIMM interface.

7. The memory module of claim 1, wherein the controller includes a buffer to store data received from the circuit.

8. The memory module of claim 1, wherein the one or more flash memory elements of the non-volatile memory subsystem include one or more of multi-level cell (MLC), NOR, ONENAND, and NAND flash memory elements.

9. The memory module of claim 1, wherein the controller is operable to provide bad-block management and error management for the one or more flash memory elements of the non-volatile memory subsystem.

10. The memory module of claim 1, wherein the standard DIMM interface includes an edge connector configured to fit into a memory socket of the host computer, the edge connector including conduits for delivery of power voltage as well as data, address, and control signals between the memory module and the host computer.

11. The memory module of claim 1, wherein the standard DIMM interface includes any one of a standard registered DIMM (RDIMM), a small-outline DIMM (SO-DIMM), unbuffered DIMM (UDIMM), mini-DIMM, mini-RDIMM, VLP mini-DIMM, and micro- DIMM.

12. A memory module comprising:

a host interface operable to be coupled to a host computer, the host interface including a standard dual inline memory module (DIMM) interface configured to be in electrical communication with the host computer using double data rate synchronous dynamic random-access memory (DDR SDRAM) data signals and DDR SDRAM address and control (addr/cont) signals;

a circuit coupled to the host interface using a data bus and an addr/cont bus, the circuit configured to be in electrical communication with the host interface (i) using DDR SDRAM data signals by way of the data bus, and (ii) using DDR SDRAM addr/cont signals by way of the addr/cont bus;

a volatile memory subsystem coupled to the circuit using a first data bus and a first addr/cont bus, the volatile memory subsystem including one or more DDR SDRAM memory elements, the volatile memory subsystem configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the first data bus, and (ii) using DDR SDRAM addr/cont signals by way of the first addr/cont bus;

a controller coupled to the circuit using a second data bus and a second addr/cont bus, the controller configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the second data bus, and (ii) using DDR SDRAM addr/cont signals by way of the second addr/cont bus; and

a non-volatile memory subsystem coupled to the controller, the non-volatile memory subsystem including one or more flash memory elements, the controller operable to (i) manage the non-volatile memory subsystem, and (ii) provide signal level translation between the one or more DDR SDRAM memory elements and the one or more flash memory elements.

13. The memory module of claim 12, wherein, in response to signals from the controller, the circuit is operable to transfer data (i) between the host computer and the volatile memory subsystem by way of the data bus and the first data bus, and (ii) between the non-volatile memory subsystem and the volatile memory subsystem by way of the first data bus and the second data bus.

14. The memory module of claim 12, further comprising:

a voltage monitor circuit coupled to the controller by way of a control signal line, the voltage monitor circuit operable to (i) monitor a supply voltage provided by the host computer to the memory module via the standard DIMM interface, (ii) generate a control signal in response to a change in the supply voltage, and (iii) transmit the control signal to the controller by way of the control signal line.

15. The memory module of claim 14, wherein, in response to the control signal, the controller is operable to control data transfer between the volatile memory subsystem and the non-volatile memory subsystem by way of the circuit, the first data bus and the second data bus.

16. The memory module of claim 15, wherein the circuit is operable to (i) receive a first set of DDR SDRAM addr/cont signals from the controller by way of the second addr/cont bus, (ii) transmit the first set of the DDR SDRAM addr/cont signals to the volatile memory subsystem by way of the first addr/cont bus, and (iii) transfer a first data signal from the volatile memory subsystem to the controller by way of the first data bus and the second data bus.

17. The memory module of claim 16, wherein a portion of the controller is dedicated to generate address and control signals for the non-volatile memory subsystem, and wherein the controller is operable to write the first data signal into the non-volatile memory subsystem using the generated address and control signals for the non-volatile memory subsystem.

18. A memory module comprising:

a host interface operable to be coupled to a host computer, the host interface inlcuding a standard dual inline memory module (DIMM) interface configured to be in electrical communication with the host computer using double data rate synchronous dynamic random-access memory (DDR SDRAM) data signals and DDR SDRAM address and control (addr/cont) signals;

a circuit coupled to the host interface using a data bus and an addr/cont bus, the circuit configured to be in electrical communication with the host interface (i) using DDR SDRAM data signals by way of the data bus, and (ii) using DDR SDRAM addr/cont signals by way of the addr/cont bus;

a volatile memory subsystem coupled to the circuit using a first data bus and a first addr/cont bus, the volatile memory subsystem including one or more DDR SDRAM memory elements, the volatile memory subsystem configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the first data bus, and (ii) using DDR SDRAM addr/cont signals by way of the first addr/cont bus;

a controller coupled to the circuit using a second data bus and a second addr/cont bus, the controller configured to be in electrical communication with the circuit (i) using DDR SDRAM data signals by way of the second data bus, and (ii) using DDR SDRAM addr/cont signals by way of the second addr/cont bus; and

a non-volatile memory subsystem coupled to the controller, the non-volatile memory subsystem including one or more flash memory elements, the controller operable to manage the non-volatile memory subsystem, and to perform address/address translation between the volatile memory subsystem and the non-volatile memory subsystem.

19. The memory module of claim 18, wherein, in response to signals from the controller, the circuit is operable to transfer data (i) between the host computer and the volatile memory subsystem by way of the data bus and the first data bus, and (ii) between the non-volatile memory subsystem and the volatile memory subsystem by way of the first data bus and the second data bus.

20. The memory module of claim 18, further comprising:

a voltage monitor circuit coupled to the controller by way of a control signal line, the voltage monitor circuit operable to (i) monitor a supply voltage provided by the host computer to the memory module via the standard DIMM interface, (ii) generate a control signal in response to a change in the supply voltage, and (iii) transmit the control signal to the controller by way of the control signal line.

21. The memory module of claim 18, wherein, in response to the control signal, the controller is operable to control data transfer between the volatile memory subsystem and the non-volatile memory subsystem by way of the circuit, the first data bus and the second data bus.

22. The memory module of claim 21, wherein the circuit is operable to (i) receive a first set of DDR SDRAM addr/cont signals from the controller by way of the second addr/cont bus, (ii) transmit the first set of the DDR SDRAM addr/cont signals to the volatile memory subsystem by way of the first addr/cont bus, and (iii) transfer a first data signal from the volatile memory subsystem to the controller by way of the first data bus and the second data bus.

23. The memory module of claim 22, wherein a portion of the controller is dedicated to generate address and control signals for the non-volatile memory subsystem, and wherein the controller is operable to write the first data signal into the non-volatile memory subsystem using the generated address and control signals for the non-volatile memory subsystem.