Semiconductor memory device

• US 9,269,445 B1
• Filed: 03/01/2015
• Issued: 02/23/2016
• Est. Priority Date: 09/17/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Abe, Kenichi, Shirakawa, Masanobu
• Primary Examiner(s): Nguyen, Hien
• Application Number:
  US14/634,873
• Publication Number:
  US 20160078949A1
• Time in Patent Office: 359 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A semiconductor memory device includes a first set of memory cells commonly connected to a first word line, a second set of memory cells commonly connected to a second word line, and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines. The writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells.

Claims

1. A semiconductor memory device comprising:

a memory cell array including a first set of memory cells commonly connected to a first word line, and a second set of memory cells commonly connected to a second word line; and

a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines, wherein the writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order;

(1) the coarse program operation on the first set of memory cells;

(2) the coarse program operation on the second set of memory cells;

(3) the fine program operation on the first set of memory cells; and

(4) the fine program operation on the second set of memory cells.

2. The device according to claim 1, wherein the coarse program operation performed on the memory cells causes the memory cells to have a threshold distribution that is wider than when the fine program operation is performed on the memory cells.

3. The device according to claim 1, wherein a first memory cell in the first set and a second memory cell in the second set are serially connected between a source side selection transistor and the a drain side selection transistor, and the first memory cell is closer to the source side selection transistor than the second memory cell.

4. The device according to claim 1, wherein the coarse program operation on the second set of memory cells is started prior to completion of the coarse program operation on the first set of memory cells.

5. The device according to claim 4, wherein the fine program operation on the second set of memory cells is started prior to completion of the fine program operation on the first set of memory cells.

6. The device according to claim 1, wherein the fine program operation on the first set of memory cells is started after completion of the coarse program operation on the second set of memory cells.

7. The device according to claim 1, wherein after the single writing operation has terminated, the control unit applies a zero voltage to the first and second word lines.

8. The device according to claim 1, wherein after the single writing operation has terminated, the control unit applies a negative voltage to the first and second word lines.

9. A semiconductor memory device comprising:

a memory cell array including a first set of memory cells commonly connected to a first word line, and a second set of memory cells commonly connected to a second word line; and

a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines, wherein the writing operation includes an initial program operation, a coarse program operation and a fine program operation, and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes performing the initial program operation on the first and second sets of memory cells, and then starting the following operations in order;

(1) the coarse program operation on the first set of memory cells;

(2) the coarse program operation on the second set of memory cells;

(3) the fine program operation on the first set of memory cells; and

(4) the fine program operation on the second set of memory cells.

10. The device according to claim 9, wherein the initial program operation performed on the memory cells causes the memory cells to have an intermediate threshold distribution.

11. The device according to claim 10, wherein the coarse program operation performed on the memory cells causes the memory cells to have a threshold distribution that is wider than when the fine program operation is performed on the memory cells.

12. The device according to claim 9, wherein a first memory cell in the first set and a second memory cell in the second set are serially connected between a source side selection transistor and the a drain side selection transistor, and the first memory cell is closer to the source side selection transistor than the second memory cell.

13. A method of performing a write operation on first and second sets of memory cells of a semiconductor memory device, wherein the first set of memory cells is commonly connected to a first word line, and the second set of memory cells is commonly connected to a second word line, said method comprising:

executing a writing operation on the first and second sets of memory cells, including controlling voltages applied to the first and second word lines, as a single write operation that includes starting the following operations in order;

(1) the coarse program operation on the first set of memory cells;

(2) the coarse program operation on the second set of memory cells;

(3) the fine program operation on the first set of memory cells; and

(4) the fine program operation on the second set of memory cells.

14. The method according to claim 13, wherein the coarse program operation performed on the memory cells causes the memory cells to have a threshold distribution that is wider than when the fine program operation is performed on the memory cells.

15. The method according to claim 13, wherein a first memory cell in the first set and a second memory cell in the second set are serially connected between a source side selection transistor and the a drain side selection transistor, and the first memory cell is closer to the source side selection transistor than the second memory cell.

16. The method according to claim 13, wherein the coarse program operation on the second set of memory cells is started prior to completion of the coarse program operation on the first set of memory cells.

17. The method according to claim 16, wherein the fine program operation on the second set of memory cells is started prior to completion of the fine program operation on the first set of memory cells.

18. The method according to claim 13, wherein the fine program operation on the first set of memory cells is started after completion of the coarse program operation on the second set of memory cells.

19. The method according to claim 13, further comprising:

after the single writing operation has terminated, applying a zero voltage to the first and second word lines.

20. The method according to claim 13, further comprising:

after the single writing operation has terminated, applying a negative voltage to the first and second word lines.