Wafer level packaging techniques
First Claim
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1. A packaged integrated circuit (IC) structure comprising:
- a first substrate comprising a CMOS device and a CMOS bond ring,a second substrate laterally extending across an outer sidewall of the first substrate, the second substrate comprising a MEMS device and a MEMS bond ring, the MEMS bond ring surrounding a periphery of the MEMS device and being bonded to the CMOS bond ring; and
a protection layer covering outer sidewalls of the MEMS bond ring and outer sidewalls of the CMOS bond ring, and further covering the outer sidewall of the first substrate and not covering an outer sidewall of the second substrate;
wherein the protection layer has an upper surface that is aligned with an upper surface of the first substrate.
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Abstract
In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.
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Citations
20 Claims
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1. A packaged integrated circuit (IC) structure comprising:
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a first substrate comprising a CMOS device and a CMOS bond ring, a second substrate laterally extending across an outer sidewall of the first substrate, the second substrate comprising a MEMS device and a MEMS bond ring, the MEMS bond ring surrounding a periphery of the MEMS device and being bonded to the CMOS bond ring; and a protection layer covering outer sidewalls of the MEMS bond ring and outer sidewalls of the CMOS bond ring, and further covering the outer sidewall of the first substrate and not covering an outer sidewall of the second substrate; wherein the protection layer has an upper surface that is aligned with an upper surface of the first substrate. - View Dependent Claims (2, 3, 4, 5)
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6. A wafer level package structure, comprising:
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a first substrate; a second substrate comprising a plurality of MEMS devices; an array of bond ring structures arranged between the first and second substrates, wherein interior sidewalls of a bond ring structure define a cavity between a first surface of the first substrate and a first surface of the second substrate; and a test line arranged on or proximate to the first surface of the second substrate, wherein the test line is arranged in a scribe line area between opposing outer sidewalls of neighboring bond ring structures and is electrically coupled to a MEMS device on the second substrate. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A packaged integrated circuit (IC) structure comprising:
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a first bond ring arranged on a first substrate and laterally set back from an outer sidewall of the first substrate; a second bond ring arranged on a second substrate and bonded to the first bond ring to enclose a hermetic cavity therebetween, wherein the second bond ring is laterally set back from an outer sidewall of the second substrate; a protection layer abutting outer sidewalls of the first and second bond rings, and not abutting the outer sidewall of the second substrate; and a through silicon via extending from a to side of the first substrate to a position within the first substrate that vertically overlies the cavity. - View Dependent Claims (17, 18, 19, 20)
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Specification