Spacer scheme for semiconductor device

• US 9,269,811 B2
• Filed: 12/26/2014
• Issued: 02/23/2016
• Est. Priority Date: 06/20/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chou, Ling-Chun, Wang, I-Chang, Hung, Ching-Wen
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US14/583,211
• Publication Number:
  US 20150108553A1
• Time in Patent Office: 424 Days
• Field of Search: 257/288, 257/410, 257/389, 257/900, 438/142, 438/181, 438/184, 438/197, 438/303, 438/304
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

Claims

1. A semiconductor device comprising:

a gate structure;

a first spacer positioned on sidewalls of the gate structure;

a second spacer positioned on the first spacer, the second spacer comprising a silicon nitride layer and a carbon-containing layer;

a SiCN-based protecting layer formed between the first spacer and the second spacer; and

epitaxial layers respectively positioned at two sides of the second spacer.

2. The semiconductor device according to claim 1, wherein the silicon nitride layer is formed by hexachlorodisilane (HCD).

3. The semiconductor device according to claim 1, wherein the carbon-containing layer is formed by a carbon source gas and hexachlorodisilane (HCD).

4. The semiconductor device according to claim 1, wherein the SiCN-based protecting layer comprises silicon oxycarbonitride (SiOCN).

5. The semiconductor device according to claim 1, wherein the SiCN-based protecting layer comprises an L shape.