Integrated circuit with pressure sensor having a pair of electrodes

• US 9,269,832 B2
• Filed: 06/11/2013
• Issued: 02/23/2016
• Est. Priority Date: 06/12/2012
• Status: Active Grant

• Current Assignee: ScioSense B.V. (Ams-Osram AG)
• Original Assignee: ams AG (Ams-Osram AG)
• Inventors: Nackaerts, Axel, Besling, Willem Frederik Adrianus, Reimann, Klaus
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US13/915,523
• Publication Number:
  US 20130328142A1
• Time in Patent Office: 987 Days
• Field of Search: 257/415, 257/E31.002, 257/E31.124, 257/418, 257/E21./158, 257/414, 438/87, 438/257, 438/53, 438/379, 438/397, 438/745, 438/542, 324/651, 324/661
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure

Abstract

Disclosed is an integrated circuit (100), comprising a semiconductor substrate (110) carrying a plurality of circuit elements; and a pressure sensor including a cavity (140) on said semiconductor substrate, said cavity comprising a pair of electrodes (120, 122) laterally separated from each other; and a flexible membrane (130) over and spatially separated from said electrodes such that said membrane interferes with a fringe field between said electrodes, said membrane comprising at least one aperture (132). A method of manufacturing such an IC is also disclosed.

Claims

1. An integrated circuit, comprising:

a semiconductor substrate carrying a plurality of circuit elements; and

a pressure sensor including a cavity on said semiconductor substrate, said cavity comprising;

a pair of electrodes laterally separated from each other; and

a flexible membrane spatially separated from said electrodes such that said flexible membrane interferes with a fringe field between said electrodes, said flexible membrane comprising at least one aperture; and

wherein the flexible membrane is not between said pair of electrodes and the flexible membrane is an electrically conductive flexible membrane.

2. The integrated circuit of claim 1, wherein at least some of said circuit elements define a capacitance measurement circuit, and wherein said electrodes are conductively coupled to said capacitance measurement circuit.

3. The integrated circuit of claim 1, wherein the electrodes are interdigitated electrodes.

4. The integrated circuit of claim 1, wherein at least one of the electrically conductive flexible membrane and the semiconductor substrate is grounded.

5. The integrated circuit of claim 1, further comprising

a capping layer over the flexible membrane, said capping layer at least partially filling the at least one aperture.

6. The integrated circuit of claim 1, further comprising

at least one patterned metallization layer for interconnecting the plurality of circuit elements and a passivation layer over the at least one patterned metallization layer, wherein each electrode of the pair of electrodes is at least partially located on the passivation layer and conductively coupled to respective portions of the at least one patterned metallization layer.

7. The integrated circuit of claim 6, wherein each of the electrodes is conductively coupled to respective portions of the at least one patterned metallization layer by respective vias extending through the passivation layer.

8. The integrated circuit of claim 1, wherein each of said electrodes comprises an electrically insulating film on the surface facing said flexible membrane.

9. The integrated circuit of claim 1, wherein said flexible membrane comprises tungsten, titanium tungsten or silicon germanium.

10. The integrated circuit of claim 4, wherein both the electrically conductive flexible membrane and the semiconductor substrate are grounded.

11. The integrated circuit of claim 4, wherein conductive material in the electrically conductive flexible membrane is tungsten.

12. An integrated circuit, comprising:

a semiconductor substrate carrying a plurality of circuit elements;

a pressure sensor including a cavity on the semiconductor substrate, the cavity comprising;

a pair of electrodes laterally separated from each other; and

a flexible membrane spatially separated from the electrodes such that the flexible membrane interferes with a fringe field between the electrodes, the flexible membrane comprising at least one aperture, wherein the flexible membrane is an electrically conductive flexible membrane; and

a capping layer over the flexible membrane, the capping layer at least partially filling the at least one aperture.

13. The integrated circuit of claim 12, wherein the flexible membrane is not between the pair of electrodes.

14. An integrated circuit, comprising:

a semiconductor substrate carrying a plurality of circuit elements;

a pressure sensor including a cavity on the semiconductor substrate, the cavity comprising;

a pair of electrodes laterally separated from each other; and

a flexible membrane spatially separated from the electrodes such that the flexible membrane interferes with a fringe field between the electrodes, the flexible membrane comprising at least one aperture, wherein the flexible membrane is an electrically conductive flexible membrane;

at least one patterned metallization layer for interconnecting the plurality of circuit elements and a passivation layer over the at least one patterned metallization layer,

wherein each electrode of the pair of electrodes is at least partially located on the passivation layer and conductively coupled to respective portions of the at least one patterned metallization layer, and

wherein the at least one patterned metallization layer is arranged over the semiconductor substrate.

15. The integrated circuit of claim 14, wherein the flexible membrane is not between the pair of electrodes.

16. The integrated circuit of claim 14, wherein each of the electrodes is conductively coupled to respective portions of the at least one patterned metallization layer by respective vias extending through the passivation layer.

17. The integrated circuit of claim 14, wherein the integrated circuit further comprises a capping layer over the flexible membrane, the capping layer at least partially filling the at least one aperture.