System for reducing noise in a chemical sensor array
First Claim
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1. A system comprising:
- a power supply;
a clock circuitry to generate a plurality of clock signals, each clock signal of the plurality of clock signals being synchronous with a primary clock signal, and the first, second, and third clock signals of the plurality of clock signals being asynchronous to each other; and
a plurality of switchers, each switcher of the plurality of switchers communicatively coupled to the power supply and the clock circuitry, whereina first switcher of the plurality of switchers receives the first clock signal, a second switcher of the plurality of switchers receives the second clock signal, and a third switcher of the plurality of switchers receives the third clock signal,the first, second and third switchers are disposed on the same substrate,the first, second, and third clock signals have different frequencies,the first clock signal has a frequency greater than a frequency of the second clock signal and the second clock signal has a frequency greater than the frequency of the third clock signal, wherein the frequency of the first clock signal is a multiple of the frequency of the second clock signal and is a multiple of the frequency of the third clock signal, anda rising edge of the first clock signal is offset in a range of ½
to (n−
1)/2 cycles of the primary clock signal, where “
n”
is the number of cycles of the primary clock signal in a cycle of the second clock signal.
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Abstract
A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.
595 Citations
14 Claims
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1. A system comprising:
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a power supply; a clock circuitry to generate a plurality of clock signals, each clock signal of the plurality of clock signals being synchronous with a primary clock signal, and the first, second, and third clock signals of the plurality of clock signals being asynchronous to each other; and a plurality of switchers, each switcher of the plurality of switchers communicatively coupled to the power supply and the clock circuitry, wherein a first switcher of the plurality of switchers receives the first clock signal, a second switcher of the plurality of switchers receives the second clock signal, and a third switcher of the plurality of switchers receives the third clock signal, the first, second and third switchers are disposed on the same substrate, the first, second, and third clock signals have different frequencies, the first clock signal has a frequency greater than a frequency of the second clock signal and the second clock signal has a frequency greater than the frequency of the third clock signal, wherein the frequency of the first clock signal is a multiple of the frequency of the second clock signal and is a multiple of the frequency of the third clock signal, and a rising edge of the first clock signal is offset in a range of ½
to (n−
1)/2 cycles of the primary clock signal, where “
n”
is the number of cycles of the primary clock signal in a cycle of the second clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 14)
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10. A method of providing power to a circuitry, the method comprising:
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supplying power with a power supply to a plurality of switcher; generating a plurality of clock signals with a clock circuitry, each of the plurality of clock signals being synchronous with a primary clock signal, and the first, second, and third clock signals of the plurality of clock signals being asynchronous to each other; and supplying the first clock signal to a first switcher, the second clock signal to a second switcher, and the third clock signal to a third switcher, the first, second and third switchers being of the plurality of switchers, wherein the first, second and third switcher are disposed on the same substrate, the first, second, and third clock signals have different frequencies, the first clock signal has a frequency greater than a frequency of the second clock signal and the second clock signal has a frequency greater than the frequency of the third clock signal, and the frequency of the first clock signal is a multiple of the frequency of the second clock signal and is a multiple of the frequency of the third clock signal, and a rising edge of the first clock signal is offset in a range of ½
to (n−
1)/2 cycles of the primary clock signal, where “
n”
is the number of cycles of the primary clock signal in a cycle of the second clock signal. - View Dependent Claims (11, 12, 13)
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Specification